Systems, methods, and devices for parallel read and write operations

A method comprising:

• receiving in a memory including a plurality of memory units, information associated with operations to be implemented in selected first and second memory units;
• configuring the selected first memory unit for a high voltage operation;
• configuring the selected second memory unit for a low voltage operation;
• and
• implementing said high and low voltage operations concurrently.

A method comprising:

• receiving in a memory including a plurality of memory units, each including a number of memory cells, information associated with a high voltage operation to be implemented in a first memory unit of the plurality of memory units;
• coupling a global bit line to a local bit line in the first memory unit, and decoupling the local bit line in the first memory unit from a sense amplifier associated with the first memory unit;
• receiving in the memory information associated with a low voltage operation to be implemented in a second memory unit of the plurality of memory units concurrently with the high voltage operation;
• and
• decoupling the global bit line from a local bit line in the second memory unit, and coupling the local bit line in the second memory unit to a sense amplifier associated with the second memory unit.

A method comprising:

• receiving in a memory including a plurality of memory units, each including a number of memory cells, information associated with a high voltage operation to be implemented in a first memory unit of the plurality of memory units;
• in response to said information associated with the high voltage operation, configuring first switching logic associated with the first memory unit to couple a global bit line to a local bit line in at least one cell in the first memory unit, and decouple the local bit line in the first memory unit from a sense amplifier associated with the first memory unit;
• receiving in the memory information associated with a low voltage operation to be implemented in a second memory unit of the plurality of memory units;
• in response to said information associated with the low voltage operation, configuring second switching logic associated with the second memory unit to decouple the global bit line from a local bit line in at least one cell in the second memory unit, and couple the local bit line in the second memory unit to a sense amplifier associated with the second memory unit;
• and
• implementing said high and low voltage operations concurrently.