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US 2017/0249976 A1Published application
Sense amplifier and latching scheme
AssigneeGlobalfoundries Inc.
InventorsVenkatraghavan Bringivijayaraghavan, Ramesh Raghavan
Life of this patent
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Abstract
Approaches for a circuit are provided. The circuit includes a sense amplifier circuit which includes a plurality of transistors enabled by a sense amplifier enable signal to output a first output data line true signal and a second output data line complement signal to a latching circuit, and the latching circuit which includes a primary driver actively driven by the first output data line true signal and a secondary driver actively driven by the second output data line complement signal such that the latching circuit outputs a read global data line.
Claims21
A circuit, comprising:
- a sense amplifier circuit which comprises a plurality of transistors enabled by a sense amplifier enable signal to output a first output data line true signal and a second output data line complement signal to a latching circuit;
- and
- the latching circuit which comprises a primary driver actively driven by the first output data line true signal and a secondary driver actively driven by the second output data line complement signal such that the latching circuit outputs a read global data line,
- wherein the secondary driver comprises a NMOS pull-up device and a PMOS pull-down device, and another transistor is directly connected between a source of the NMOS pull-up device and a source of the PMOS pull-down device, and
- a source of the another transistor is directly connected to the source of the NMOS pull-up device, a drain of the another transistor is directly connected to the source of the PMOS pull-down device, and a gate of the another transistor is directly connected to an inverted signal of the sense amplifier enable signal.
2 more elements
(canceled)
A circuit, comprising:
- a sense amplifier circuit which comprises a plurality of transistors enabled by a sense amplifier enable signal to output a first output data line true signal and a second output data line complement signal to a latching circuit;
- the latching circuit which comprises a PMOS pull-up device and a NMOS pull-down device which are actively driven by the first output data line true signal and a NMOS pull-up device and a PMOS pull-down device which are actively driven by the second output data line complement signal such that the latching circuit outputs a read global data line;
- and
- another transistor which is directly connected between a source of the NMOS pull-up device and a source of the PMOS pull-down device.
- wherein a source of the another transistor is directly connected to the source of the NMOS pull-up device, a drain of the another transistor is directly connected to the source of the PMOS pull-down device, and a gate of the another transistor is directly connected to an inverted signal of the sense amplifier enable signal.
2 more elements
A method, comprising:
- enabling a sense amplifier circuit to output a first output data line true signal and a second output data line complement signal to a latching circuit;
- actively driving a primary driver of the latching circuit by the first output data line true signal;
- actively driving a secondary driver of the latching circuit by the second output data line complement signal;
- and
- outputting a read global data line based on the primary driver and the secondary driver being actively driven through another transistor which is connected between a source of a NMOS pull-up device of the secondary driver and a source of a PMOS pull-down device of the secondary driver,
- wherein a source of the another transistor is directly connected to the source of the NMOS pull-up device, a drain of the another transistor is directly connected to the source of the PMOS pull-down device, and a gate of the another transistor is directly connected to an inverted signal of a sense amplifier enable signal.
3 more elements
(canceled)
Dependencies are inferred from the claim text.