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US 2017/0249918 A1Published application
Method for driving display device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsHajime KIMURA, Atsushi UMEZAKI
Life of this patent
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Abstract
To suppress degradation of a transistor. A method for driving a liquid crystal display device has a first period and a second period. In the first period, a first transistor and a second transistor are alternately turned on and off repeatedly, and a third transistor and a fourth transistor are turned off. In the second period, the first transistor and the second transistor are turned off, and the third transistor and the fourth transistor are alternately turned on and off repeatedly. Accordingly, the time during which the transistor is on can be reduced, so that degradation of characteristics of the transistor can be suppressed.
Claims17
(canceled)
A semiconductor device comprising:
- a first transistor, a second transistor and a third transistor,
- wherein one of source and drain of the first transistor is electrically connected to a first wiring,
- wherein the other of source and drain of the first transistor is electrically connected to a second wiring,
- wherein one of source and drain of the second transistor is electrically connected to a gate of the first transistor,
- wherein the other of source and drain of the second transistor is electrically connected to the second wiring,
- wherein one of source and drain of the third transistor is electrically connected to the gate of the first transistor,
- wherein the other of source and drain of the third transistor is electrically connected to the second wiring, and
- wherein a first clock signal is input to the first wiring.
5 more elements
A semiconductor device comprising:
- a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor,
- wherein one of source and drain of the first transistor is electrically connected to a first wiring,
- wherein the other of source and drain of the first transistor is electrically connected to a second wiring,
- wherein one of source and drain of the second transistor is electrically connected to a gate of the first transistor,
- wherein the other of source and drain of the second transistor is electrically connected to the second wiring,
- wherein one of source and drain of the third transistor is electrically connected to the gate of the first transistor,
- wherein the other of source and drain of the third transistor is electrically connected to the second wiring,
- wherein one of source and drain of the fourth transistor is electrically connected to a third wiring,
- wherein the other of source and drain of the fourth transistor is electrically connected to a fourth wiring,
- wherein one of source and drain of the fifth transistor is electrically connected to a gate of the fourth transistor,
- wherein the other of source and drain of the fifth transistor is electrically connected to the fourth wiring,
- wherein one of source and drain of the sixth transistor is electrically connected to the gate of the fourth transistor,
- wherein the other of source and drain of the sixth transistor is electrically connected to the fourth wiring,
- wherein one of source and drain of the seventh transistor is electrically connected to the second wiring,
- wherein the other of source and drain of the seventh transistor is electrically connected to the gate of the fourth transistor, and
- wherein a first clock signal is input to the first wiring, and a second clock signal is input to the second wiring.
13 more elements
A semiconductor device comprising:
- a first transistor, a second transistor and a third transistor,
- wherein one of source and drain of the first transistor is electrically connected to a first wiring,
- wherein the other of source and drain of the first transistor is electrically connected to a second wiring,
- wherein one of source and drain of the second transistor is electrically connected to a gate of the first transistor,
- wherein the other of source and drain of the second transistor is electrically connected to the second wiring,
- wherein one of source and drain of the third transistor is electrically connected to the gate of the first transistor,
- wherein the other of source and drain of the third transistor is electrically connected to the second wiring,
- wherein a first clock signal is input to the first wiring, and
- wherein a channel width of the second transistor is approximately equal to a channel width of the third transistor.
6 more elements
A semiconductor device comprising:
- a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor,
- wherein one of source and drain of the first transistor is electrically connected to a first wiring,
- wherein the other of source and drain of the first transistor is electrically connected to a second wiring,
- wherein one of source and drain of the second transistor is electrically connected to a gate of the first transistor,
- wherein the other of source and drain of the second transistor is electrically connected to the second wiring,
- wherein one of source and drain of the third transistor is electrically connected to the gate of the first transistor,
- wherein the other of source and drain of the third transistor is electrically connected to the second wiring,
- wherein one of source and drain of the fourth transistor is electrically connected to a third wiring,
- wherein the other of source and drain of the fourth transistor is electrically connected to a fourth wiring,
- wherein one of source and drain of the fifth transistor is electrically connected to a gate of the fourth transistor,
- wherein the other of source and drain of the fifth transistor is electrically connected to the fourth wiring,
- wherein one of source and drain of the sixth transistor is electrically connected to the gate of the fourth transistor,
- wherein the other of source and drain of the sixth transistor is electrically connected to the fourth wiring,
- wherein one of source and drain of the seventh transistor is electrically connected to the second wiring,
- wherein the other of source and drain of the seventh transistor is electrically connected to the gate of the fourth transistor,
- wherein a first clock signal is input to the first wiring, and a second clock signal is input to the second wiring, and
- wherein a channel width of the second transistor is approximately equal to a channel width of the third transistor, and a channel width of the fifth transistor is approximately equal to a channel width of the sixth transistor.
14 more elements
A semiconductor device comprising:
- a first transistor, a second transistor and a third transistor, each including an oxide semiconductor layer, a first conductive layer and a gate insulating layer interposed between the oxide semiconductor layer and the first conductive layer,
- wherein a thickness of the oxide semiconductor layer is smaller than a thickness of the gate insulating layer,
- wherein one of source and drain of the first transistor is electrically connected to a first wiring,
- wherein the other of source and drain of the first transistor is electrically connected to a second wiring,
- wherein one of source and drain of the second transistor is electrically connected to a gate of the first transistor,
- wherein the other of source and drain of the second transistor is electrically connected to the second wiring,
- wherein one of source and drain of the third transistor is electrically connected to the gate of the first transistor,
- wherein the other of source and drain of the third transistor is electrically connected to the second wiring, and
- wherein a first clock signal is input to the first wiring.
6 more elements
A semiconductor device comprising:
- a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, each including an oxide semiconductor layer, a first conductive layer and a gate insulating layer interposed between the oxide semiconductor layer and the first conductive layer,
- wherein a thickness of the oxide semiconductor layer is smaller than a thickness of the gate insulating layer,
- wherein one of source and drain of the first transistor is electrically connected to a first wiring,
- wherein the other of source and drain of the first transistor is electrically connected to a second wiring,
- wherein one of source and drain of the second transistor is electrically connected to a gate of the first transistor,
- wherein the other of source and drain of the second transistor is electrically connected to the second wiring,
- wherein one of source and drain of the third transistor is electrically connected to the gate of the first transistor,
- wherein the other of source and drain of the third transistor is electrically connected to the second wiring,
- wherein one of source and drain of the fourth transistor is electrically connected to a third wiring,
- wherein the other of source and drain of the fourth transistor is electrically connected to a fourth wiring,
- wherein one of source and drain of the fifth transistor is electrically connected to a gate of the fourth transistor,
- wherein the other of source and drain of the fifth transistor is electrically connected to the fourth wiring,
- wherein one of source and drain of the sixth transistor is electrically connected to the gate of the fourth transistor,
- wherein the other of source and drain of the sixth transistor is electrically connected to the fourth wiring,
- wherein one of source and drain of the seventh transistor is electrically connected to the second wiring,
- wherein the other of source and drain of the seventh transistor is electrically connected to the gate of the fourth transistor, and
- wherein a first clock signal is input to the first wiring, and a second clock signal is input to the second wiring.
14 more elements
A semiconductor device comprising:
- a first transistor, a second transistor and a third transistor, each including an oxide semiconductor layer, a first conductive layer and a gate insulating layer interposed between the oxide semiconductor layer and the first conductive layer,
- wherein a thickness of the gate insulating layer is larger than a thickness of the first conductive layer,
- wherein one of source and drain of the first transistor is electrically connected to a first wiring,
- wherein the other of source and drain of the first transistor is electrically connected to a second wiring,
- wherein one of source and drain of the second transistor is electrically connected to a gate of the first transistor,
- wherein the other of source and drain of the second transistor is electrically connected to the second wiring,
- wherein one of source and drain of the third transistor is electrically connected to the gate of the first transistor,
- wherein the other of source and drain of the third transistor is electrically connected to the second wiring, and
- wherein a first clock signal is input to the first wiring.
6 more elements
A semiconductor device comprising:
- a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, each including an oxide semiconductor layer, a first conductive layer and a gate insulating layer interposed between the oxide semiconductor layer and the first conductive layer,
- wherein a thickness of the gate insulating layer is larger than a thickness of the first conductive layer,
- wherein one of source and drain of the first transistor is electrically connected to a first wiring,
- wherein the other of source and drain of the first transistor is electrically connected to a second wiring,
- wherein one of source and drain of the second transistor is electrically connected to a gate of the first transistor,
- wherein the other of source and drain of the second transistor is electrically connected to the second wiring,
- wherein one of source and drain of the third transistor is electrically connected to the gate of the first transistor,
- wherein the other of source and drain of the third transistor is electrically connected to the second wiring,
- wherein one of source and drain of the fourth transistor is electrically connected to a third wiring,
- wherein the other of source and drain of the fourth transistor is electrically connected to a fourth wiring,
- wherein one of source and drain of the fifth transistor is electrically connected to a gate of the fourth transistor,
- wherein the other of source and drain of the fifth transistor is electrically connected to the fourth wiring,
- wherein one of source and drain of the sixth transistor is electrically connected to the gate of the fourth transistor,
- wherein the other of source and drain of the sixth transistor is electrically connected to the fourth wiring,
- wherein one of source and drain of the seventh transistor is electrically connected to the second wiring,
- wherein the other of source and drain of the seventh transistor is electrically connected to the gate of the fourth transistor, and
- wherein a first clock signal is input to the first wiring, and a second clock signal is input to the second wiring.
14 more elements
Dependencies are inferred from the claim text.