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US 2017/0249907 A1Published application
Scanning drive circuit and display device including the same
AssigneeSony Corporation
InventorsTakao Tanikame, Seiichiro Jinta
Life of this patent
Estimating the term…
Abstract
Disclosed herein is a display device, including display elements two-dimensionally disposed in a matrix; scanning lines, initialization control lines, and display control lines extending in a first direction; data lines extending in a second direction different from the first direction; and a scanning drive circuit.
Claims12
A display device, comprising:
- a display area including a plurality of pixel circuits;
- a peripheral area including a scanning circuit;
- a plurality of first scanning lines;
- a plurality of second scanning lines;
- and
- a plurality of third scanning lines;
- wherein
- the scanning circuit facing to a first side of the display area is configured to receive an input pulse and supply a plurality of output signals,
- each of the plurality of pixel circuits includes a write transistor, a drive transistor, a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a capacitor, and a light emitting element, wherein a duration of a light emitting period of respective light emitting element in each of the pixel circuits within one frame period is variably controlled by changing a width of the input pulse,
- an initializing potential is supplied from an initializing voltage line to the capacitor via the second switching transistor,
- a data potential is supplied from a video signal line to the capacitor via the write transistor, the drive transistor, and the first switching transistor,
- a drive current is supplied from a voltage line to the light emitting element via the third switching transistor, the drive transistor, and the fourth switching transistor,
- a gate terminal of the third switching transistor and a gate terminal of the fourth switching transistor are connected to the scanning circuit via one of the plurality of first scanning lines,
- a gate terminal of the write transistor and a gate terminal of the first switching transistor are connected to the scanning circuit via one of the plurality of second scanning lines, and
- a gate terminal of the second switching transistor is connected to the scanning circuit via one of the plurality of third scanning lines.
12 more elements
A display device, comprising:
- a display area including a plurality of pixel circuits;
- a peripheral area including a scanning circuit;
- a plurality of first scanning lines;
- a plurality of second scanning lines;
- and
- a plurality of third scanning lines;
- wherein
- the scanning circuit facing to a first side of the display area is configured to receive an input pulse and supply a plurality of output signals,
- each of the plurality of pixel circuits includes a write transistor, a drive transistor, a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a capacitor, and a light emitting element, wherein a duration of a light emitting period of respective light emitting element in each of the pixel circuits within one frame period is variably controlled by changing a width of the input pulse,
- an initializing potential is supplied from an initializing voltage line to the capacitor via the second switching transistor,
- a data potential is supplied from a video signal line to the capacitor via the write transistor, the drive transistor, and the first switching transistor during a non-display time period,
- a drive current is supplied from a voltage line to the light emitting element via the third switching transistor, the drive transistor, and the fourth switching transistor during a display time period,
- a gate terminal of the third switching transistor and a gate terminal of the fourth switching transistor are connected to the scanning circuit via one of the plurality of first scanning lines,
- a gate terminal of the write transistor and a gate terminal of the first switching transistor are connected to the scanning circuit via one of the plurality of second scanning lines,
- a gate terminal of the second switching transistor is connected to the scanning circuit via one of the plurality of third scanning lines, and
- a ratio between the display time period and the non-display time period is adjusted by changing the width of the input pulse.
13 more elements
Dependencies are inferred from the claim text.