Semiconductor device

A semiconductor device including a data driver for driving a display device having an n (n is an integer of 2 or more) number of data lines in accordance with a video signal, the semiconductor device comprising:

• a shift register for generating a latch timing signal on a basis of a start pulse and a clock signal;
• data register latches each for latching and outputting a pixel data signal of each pixel represented by the video signal in synchronization with the latch timing signal on a predetermined number basis;
• a level shift circuit group for applying a level change process to each of the n number of pixel data signals outputted from the data register latches to increase a signal level, and generating an n number of level changed pixel data signals;
• a decoder circuit group for selecting an N (N is an integer of 1 or more) number of reference voltages corresponding to the respective level changed pixel data signals, out of a plurality of reference voltages different from each other, and generating an N number of reference voltage signals corresponding to the selected reference voltages;
• and
• an output circuit group including an n number of output circuits corresponding to the n number of data lines of the display device, each of the output circuits amplifying a weighted average voltage of the N number of reference voltage signals to generate an output signal and supplying the output signal to the corresponding data line of the display device, wherein:
• each of the output circuits includes
• first to Nth input terminals for receiving the N number of reference voltage signals as first to Nth input signals, and an output terminal for outputting the output signal, and
• a differential input stage, an output amplifier stage, and an amplification accelerator circuit for accelerating an amplification operation of the output amplifier stage;
• the differential input stage includes
• first conductivity-type first to Nth differential stages for generating first to Nth pairs of currents each of which corresponds to a difference between each of the first to Nth input signals and the output signal, and for flowing one of each of the first to Nth pairs of currents into a first common wire and flowing the other of each of the first to Nth pairs of currents into a second common wire,
• second conductivity-type (N+1)th to (2N)th differential stages for generating (N+1)th to (2N)th pairs of currents each of which corresponds to the difference between each of the first to Nth input signals and the output signal, and for flowing one of each of the (N+1)th to (2N)th pairs of currents into a third common wire and flowing the other of each of the (N+1)th to (2N)th pairs of currents into a fourth common wire,
• a first current mirror connected between a first power supply terminal and first and second nodes, the first current mirror including a pair of second conductivity-type transistors that are connected to the first and second common wires at one ends, respectively, and connected to each other at control terminals, the first current mirror including a current input portion for flowing a current into one of the pair of second conductivity-type transistors in accordance with a current flowing through the first common wire and the second node and a current output portion for flowing a current into the other of the pair of second conductivity-type transistors in accordance with the current flowing through the one of the pair of second conductivity-type transistors,
• a second current mirror connected between a second power supply terminal and third and fourth nodes, the second current mirror including a pair of first conductivity-type transistors that are connected to the third and fourth common wires at one ends, respectively, and connected to each other at control terminals, the second current mirror including a current input portion for flowing a current into one of the pair of first conductivity-type transistors in accordance with a current flowing through the third common wire and the fourth node and a current output portion for flowing a current into the other of the pair of first conductivity-type transistors in accordance with the current flowing through the one of the pair of first conductivity-type transistors,
• a first floating current supply circuit connected between the second node to which an input node of the first current mirror is connected and the fourth node to which an input node of the second current mirror is connected, and
• a second floating current supply circuit connected between the first node to which an output node of the first current mirror is connected and the third node to which an output node of the second current mirror is connected;
• the output amplifier stage includes
• a second conductivity-type first output transistor connected between a third power supply terminal and the output terminal, and connected to the first node at a control terminal, and
• a first conductivity-type second output transistor connected between a fourth power supply terminal and the output terminal, and connected to the third node at a control terminal;
• the amplification accelerator circuit includes first and second output nodes for outputting currents;
• when a weighted average voltage of the first to Nth input signals determined in accordance with a weighting ratio of each of the first to Nth differential stages and the (N+1)th to (2N)th differential stages is higher than a voltage of the output signal, the amplification accelerator circuit outputs a current from the first output node to add the current to a current flowing through the current output portion of the second current mirror, while cutting off a current output from the second output node;
• when the weighted average voltage is lower than the voltage of the output signal, the amplification accelerator circuit outputs a current from the second output node to add the current to a current flowing through the current output portion of the first current mirror, while cutting off a current output from the first output node;
• and
• when the weighted average voltage is equal to the voltage of the output signal, the amplification accelerator circuit cuts off current outputs from both of the first and second output nodes.

A semiconductor device comprising:

• an output circuit including a differential input stage, an output amplifier stage, first to Nth (N is a positive integer of 1 or more) input terminals, and an output terminal for outputting an output signal;
• and
• an amplification accelerator circuit for accelerating an amplification operation of the output amplifier stage, wherein:
• the differential input stage includes
• first conductivity-type first to Nth differential stages for generating first to Nth pairs of currents each of which corresponds to a difference between each of the first to Nth input signals supplied to the respective first to Nth input terminals and the output signal, and for flowing one of each of the first to Nth pairs of currents into a first common wire and flowing the other of each of the first to Nth pairs of currents into a second common wire,
• second conductivity-type (N+1)th to (2N)th differential stages for generating (N+1)th to (2N)th pairs of currents each of which corresponds to the difference between each of the first to Nth input signals and the output signal, and for flowing one of each of the (N+1)th to (2N)th pairs of currents into a third common wire and flowing the other of each of the (N+1)th to (2N)th pairs of currents into a fourth common wire,
• a first current mirror connected between a first power supply terminal and first and second nodes, the first current mirror including a pair of second conductivity-type transistors that are connected to the first and second common wires at one ends, respectively, and connected to each other at control terminals, the first current mirror including a current input portion for flowing a current into one of the pair of second conductivity-type transistors in accordance with a current flowing through the first common wire and the second node and a current output portion for flowing a current into the other of the pair of second conductivity-type transistors in accordance with the current flowing through the one of the pair of second conductivity-type transistors,
• a second current mirror connected between a second power supply terminal and third and fourth nodes, the second current mirror including a pair of first conductivity-type transistors that are connected to the third and fourth common wires at one ends, respectively, and connected to each other at control terminals, the second current mirror including a current input portion for flowing a current into one of the pair of first conductivity-type transistors in accordance with a current flowing through the third common wire and the fourth node and a current output portion for flowing a current into the other of the pair of first conductivity-type transistors in accordance with the current flowing through the one of the pair of first conductivity-type transistors,
• a first floating current supply circuit connected between the second node to which an input node of the first current mirror is connected and the fourth node to which an input node of the second current mirror is connected, and
• a second floating current supply circuit connected between the first node to which an output node of the first current mirror is connected and the third node to which an output node of the second current mirror is connected;
• the output amplifier stage includes
• a second conductivity-type first output transistor connected between a third power supply terminal and the output terminal, and connected to the first node at a control terminal, and
• a first conductivity-type second output transistor connected between a fourth power supply terminal and the output terminal, and connected to the third node at a control terminal;
• the amplification accelerator circuit includes first and second output nodes for outputting currents;
• when a weighted average voltage of an M (M is an integer of 1 to N) number of input signals of the first to Nth input signals determined in accordance with a weighting ratio of each of the first to Nth differential stages and the (N+1)th to (2N)th differential stages is higher than a voltage of the output signal, the amplification accelerator circuit outputs a current from the first output node to add the current to a current flowing through the current output portion of the second current mirror, while cutting off a current output from the second output node;
• when the weighted average voltage is lower than the voltage of the output signal, the amplification accelerator circuit outputs a current from the second output node to add the current to a current flowing through the current output portion of the first current mirror, while cutting off a current output from the first output node;
• and
• when the weighted average voltage is equal to the voltage of the output signal, the amplification accelerator circuit cuts off current outputs from both of the first and second output nodes.

A semiconductor device including a data driver for driving a display device having an n (n is an integer of 2 or more) number of data lines in accordance with a video signal, the semiconductor device comprising:

• a shift register for generating a latch timing signal on a basis of a start pulse and a clock signal;
• data register latches each for latching and outputting a pixel data signal of each pixel represented by the video signal in synchronization with the latch timing signal on a predetermined number basis;
• a level shift circuit group for applying a level change process to each of the n number of pixel data signals outputted from the data register latches to increase a signal level, and generating an n number of level changed pixel data signals;
• a decoder circuit group for selecting an N (N is an integer of 1 or more) number of reference voltages corresponding to the respective level changed pixel data signals, out of a plurality of reference voltages different from each other, and generating an N number of reference voltage signals corresponding to the selected reference voltages;
• and
• an output circuit group including an n number of output circuits corresponding to the n number of data lines of the display device, each of the output circuits amplifying a weighted average voltage of the N number of reference voltage signals to generate an output signal and supplying the output signal to the corresponding data line of the display device, wherein:
• each of the output circuits includes
• first to Nth input terminals for receiving the N number of reference voltage signals as first to Nth input signals, and an output terminal for outputting the output signal, and
• a differential input stage, an output amplifier stage, and an amplification accelerator circuit for accelerating an amplification operation of the output amplifier stage;
• the differential input stage includes
• first conductivity-type first to Nth differential stages for generating first to Nth pairs of currents each of which corresponds to a difference between each of the first to Nth input signals and the output signal, and for flowing one of each of the first to Nth pairs of currents into a first common wire and flowing the other of each of the first to Nth pairs of currents into a second common wire,
• second conductivity-type (N+1)th to (2N)th differential stages for generating (N+1)th to (2N)th pairs of currents each of which corresponds to the difference between each of the first to Nth input signals and the output signal, and for flowing one of each of the (N+1)th to (2N)th pairs of currents into a third common wire and flowing the other of each of the (N+1)th to (2N)th pairs of currents into a fourth common wire,
• a first current mirror connected between a first power supply terminal and first and second nodes, the first current mirror including a pair of second conductivity-type transistors that are connected to the first and second common wires at one ends, respectively, and connected to each other at control terminals, the first current mirror including a current input portion for flowing a current into one of the pair of second conductivity-type transistors in accordance with a current flowing through the first common wire and the second node and a current output portion for flowing a current into the other of the pair of second conductivity-type transistors in accordance with the current flowing through the one of the pair of second conductivity-type transistors,
• a second current mirror connected between a second power supply terminal and third and fourth nodes, the second current mirror including a pair of first conductivity-type transistors that are connected to the third and fourth common wires at one ends, respectively, and connected to each other at control terminals, the second current mirror including a current input portion for flowing a current into one of the pair of first conductivity-type transistors in accordance with a current flowing through the third common wire and the fourth node and a current output portion for flowing a current into the other of the pair of first conductivity type transistors in accordance with the current flowing through the one of the pair of first conductivity-type transistors,
• a first floating current supply circuit connected between the second node to which an input node of the first current mirror is connected and the fourth node to which an input node of the second current mirror is connected, and
• a second floating current supply circuit connected between the first node to which an output node of the first current mirror is connected and the third node to which an output node of the second current mirror is connected;
• the output amplifier stage includes
• a second conductivity-type first output transistor connected between a third power supply terminal and the output terminal, and connected to the first node at a control terminal, and
• a first conductivity-type second output transistor connected between a fourth power supply terminal and the output terminal, and connected to the third node at a control terminal;
• the amplification accelerator circuit includes first and second output nodes for outputting currents;
• when a weighted average voltage of an M (M is an integer of 1 to N) number of input signals of the first to Nth input signals determined in accordance with a weighting ratio of each of the first to Nth differential stages and the (N+1)th to (2N)th differential stages is higher than a voltage of the output signal, the amplification accelerator circuit outputs a current from the first output node to add the current to a current flowing through the current output portion of the second current mirror, while cutting off a current output from the second output node;
• when the weighted average voltage is lower than the voltage of the output signal, the amplification accelerator circuit outputs a current from the second output node to add the current to a current flowing through the current output portion of the first current mirror, while cutting off a current output from the first output node;
• and
• when the weighted average voltage is equal to the voltage of the output signal, the amplification accelerator circuit cuts off current outputs from both of the first and second output nodes.