Reuse of extracted layout-dependent effects for circuit design using circuit stencils

A computer-implemented method, comprising:

• receiving a schematic of a first integrated circuit comprising a circuit segment;
• instantiating a circuit stencil corresponding to the circuit segment in a schematic of a second integrated circuit, the circuit stencil comprising layout-dependent effects information for the circuit segment extracted from a layout of the first integrated circuit;
• performing simulation on the schematic of the second integrated circuit using the layout-dependent effects information for the circuit segment;
• and
• generating a layout of at least a portion of the second integrated circuit corresponding to the circuit segment responsive to performing the simulation.

A computer-implemented method, comprising:

• receiving a schematic of a first integrated circuit comprising a circuit segment;
• performing simulation on a schematic of a second integrated circuit containing the circuit segment by at least referencing layout-dependent effects information for the circuit segment in a circuit stencil corresponding to the circuit segment, the layout-dependent effects information for the circuit segment extracted from a layout of the first integrated circuit;
• and
• generating a layout of at least a portion of the second integrated circuit corresponding to the circuit segment responsive to performing the simulation.

A non-transitory computer-readable storage medium storing instructions thereon, the instructions when executed by a processor cause the processor to:

• receive a schematic of a first integrated circuit comprising a circuit segment;
• instantiate a circuit stencil corresponding to the circuit segment in a schematic of a second integrated circuit, the circuit stencil comprising layout-dependent effects information for the circuit segment extracted from a layout of the first integrated circuit;
• perform simulation on the schematic of the second integrated circuit using the layout-dependent effects information for the circuit segment;
• and
• generate a layout of at least a portion of the second integrated circuit corresponding to the circuit segment responsive to performing the simulation.