Riser matrix
AssigneeHewlett Packard Enterprise Development LP
InventorsHung-Chu LEE, Tse-Jen SUNG, Chui Ching CHIU, Kang-Jong PENG, Vincent NGUYEN, Jim KUO
Life of this patent
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Abstract
A computing system for dynamically changing at least one input/output configuration between a motherboard of a computing device and at least one node connected to the motherboard includes a plurality of interchangeable topology transformation units (TTU) risers to connect at least one processing device located on a motherboard of the computing system to a plurality of computing nodes. Each of the TTU risers include topologies designed to support different workloads with respect to another TTU riser.
Claims15
A system for dynamically transforming the topology of a computing system comprising:
- a first topology transformation unit (TTU) riser to connect at least one processing device located on a motherboard of the computing system to a plurality of computing devices;
- and
- wherein the first TTU riser is replaceable by a second TTU riser without rendering other elements of the system inoperable.
A computing system for dynamically changing at least one input/output configuration between a motherboard of a computing device and at least one node connected to the motherboard, comprising:
- at least one interchangeable topology transformation unit (TTU) riser to connect at least one processing device located on a motherboard of the computing system to a plurality of computing nodes:
- wherein, the at least one TTU riser comprises a topology designed to support at least one workload that is different with respect to a second TTU riser.
A method of changing an input/output configuration of a computing system comprising:
- transmitting signals to the at least one computing device based on a topology of a first TTU riser installed in an interface, the interface to couple at least one interchangeable topology transformation units (TTU) riser to at least one processing device located on a motherboard of the computing system to a plurality of computing devices without intermediary printed circuit board (PCB) layers or interconnect busses;
- wherein, each of the TTU risers comprise topologies designed to support different workloads with respect to another TTU riser.
Dependencies are inferred from the claim text.