High Speed, Parallel Configuration of Multiple Field Programmable Gate Arrays

A system comprising:

• a host computing system comprising:
• a host memory storing a first configuration bit image for a first application;
• and
• a host processor adapted to transmit a first message comprising a first memory address of the first configuration bit image in the host memory;
• one or more nonvolatile memories, each nonvolatile memory storing a second configuration bit image for a communication functionality;
• and
• a one or more primary field programmable gate arrays, each primary field programmable gate array coupled to the host processor and coupled to a nonvolatile memory of the one or more nonvolatile memories, each primary field programmable gate array configured for the communication functionality using the second configuration bit image, each primary field programmable gate array having a DMA engine and, in response to the first message, configured to use the DMA engine to access the host memory, obtain the first configuration bit image, and to self-configure for the first application using the first configuration bit image.

A system comprising:

• a PCIe switch;
• a plurality of PCIe communication lines coupled to the PCIe switch;
• a host computing system comprising:
• a host memory storing a first configuration bit image for a application;
• and
• a host processor adapted to transmit a message comprising a memory address of the first configuration bit image in the host memory;
• one or more nonvolatile memories, each nonvolatile memory storing a second configuration bit image for a communication functionality;
• a plurality of JTAG communication lines;
• a plurality of primary field programmable gate arrays, each primary field programmable gate array coupled to a PCIe communication line of the plurality of PCIe communication lines and to one or more JTAG communication lines of the plurality of JTAG communication lines;
• each primary field programmable gate array coupled to a nonvolatile memory, each primary field programmable gate array configured for the communication functionality using the second configuration bit image, each primary field programmable gate array having a DMA engine and, in response to the message, to use the DMA engine to access the host memory, obtain the first configuration bit image, and self-configure for the application using the first configuration bit image;
• each primary field programmable gate array configured to transmit the first configuration bit image over the one or more corresponding JTAG communication lines;
• and
• a plurality of secondary field programmable gate arrays, each secondary field programmable gate array coupled to a JTAG communication line of the plurality of JTAG communication lines, each secondary field programmable gate configured for the application using the first configuration bit image transmitted over the plurality of JTAG communication lines.