Memory controller and integrated circuit system

A memory controller comprising:

• a plurality of ports coupled with at least one host device;
• a plurality of channels coupled with at least one memory device;
• an arbiter suitable for receiving at least one first address received through the plurality of ports, and outputting the first address;
• a mapping table storage block including a plurality of address mapping tables, suitable for selecting an address mapping table corresponding to the first address among the plurality of address mapping tables and outputting the selected address mapping table as a variable address mapping table;
• an address mapping block suitable for mapping the first address to a second address according to the variable address mapping table;
• and
• a scheduler suitable for outputting the second address to the channels.

An integrated circuit system comprising:

• a plurality of host devices;
• a plurality of memory devices;
• and
• a memory controller including a plurality of address mapping tables, suitable for mapping a first address received from at least one host device among the plurality of host devices, to a second address, by using an address mapping table selected among the plurality of address mapping tables and a fixed address mapping table, and transmitting the second address to at least one memory device among the plurality of memory devices.