System and method for improved memory performance using cache level hashing
AssigneeQUALCOMM Incorporated
InventorsFeng WANG, Bohuslav RYCHLIK
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AssigneeQUALCOMM Incorporated
InventorsFeng WANG, Bohuslav RYCHLIK
Estimating the term…
Various embodiments of methods and systems for cache-level memory management in a system on a chip (“SoC”) are disclosed. Memory utilization is optimized in certain embodiments through application of customized hashing algorithms at the lower level cache of individual application clients. Advantageously, for those application clients that do not require or benefit from hashing transaction traffic their transactions are not subjected to hashing. For those application clients that do benefit from hashing transaction traffic in order to minimize page conflicts at a double data rate (“DDR”) memory device, each client further benefits from a customized, and thus optimized, hashing algorithm. Because transaction streams arrive at the memory controller already hashed, or purposefully unhashed, the need for validating clients during a development phase is minimized.
A method for cache-level memory management in a system on a chip (“SoC”), the method comprising:
A system for cache-level memory management in a system on a chip (“SoC”), the system comprising:
A system for cache-level memory management in a system on a chip (“SoC”), the system comprising:
A computer program product comprising a non-transitory computer usable device having a computer readable program code embodied therein, said computer readable program code adapted to be executed to implement a method for cache-level memory management in a system on a chip (“SoC”), said method comprising:
Dependencies are inferred from the claim text.