Memory device, and information-processing device
AssigneeKabushiki Kaisha Toshiba
InventorsYuji IZUMI, Kenichi MAEDA, Kenji FUNAOKA, Reina NISHINO, Toshio FUJISAWA, Nobuhiro KONDO
Life of this patent
Estimating the term…
Abstract
According to one embodiment, the memory device includes a non-volatile memory, a volatile memory, and a controller. The controller carries out the transition to two different sleep states depending on a sleep instruction from the host device and saves sleep state information indicating the sleep state after the transition to the host-side storage device. Upon receiving a return instruction from the host device, the controller carries out return processing in accordance with the sleep state information stored in the host-side storage device.
Claims20
A memory device connected to a host device having a host-side storage device, the memory device comprising:
- a non-volatile memory;
- a volatile memory that stores data written to or read from the non-volatile memory and stores management information which manages a storage location of the data stored in the non-volatile memory;
- and
- a controller that transfers data between the non-volatile memory and the volatile memory based on an instruction from the host device,
- wherein the controller:
- carries out the transition to two different sleep states depending on a sleep instruction from the host device;
- saves sleep state information indicating the sleep state after the transition to the host-side storage device;
- and
- carries out, upon receiving a return instruction from the host device, return processing in accordance with the sleep state information stored in the host-side storage device.
A memory device connected to a host device having a host-side storage device, the memory device comprising:
- a first non-volatile memory;
- a volatile memory that stores data written to or read from the first non-volatile memory and stores management information which manages a storage location of the data stored in the first non-volatile memory;
- a controller that transfers data between the first non-volatile memory and the volatile memory based on an instruction from the host device;
- and
- a second non-volatile memory that stores sleep state support information indicating whether the memory device supports a sleep state, the sleep state being a state in which the power supplies for the first non-volatile memory, the volatile memory, the controller, and the second non-volatile memory are shut off and information stored in the volatile memory is saved to the host-side storage device,
- wherein the controller:
- carries out the transition to the sleep state depending on a sleep instruction from the host device;
- and
- upon receiving a return instruction from the host device, refers to the sleep state support information in the second non-volatile memory and when the sleep state not supported, carries out startup processing of the first non-volatile memory without waiting for link layer establishment processing relative to the host device.
An information-processing device comprising:
- a host device having a host-side storage device;
- and
- a memory device connected to the host device, wherein
- the memory device includes:
- a non-volatile memory;
- a volatile memory that stores data written to or read from the non-volatile memory and stores management information which manages a storage location of the data stored in the non-volatile memory;
- and
- a controller that transfers data between the non-volatile memory and the volatile memory based on an instruction from the host device, and
- the controller:
- carries out the transition to two different sleep states depending on a sleep instruction from the host device;
- saves sleep state information indicating the sleep state after the transition to the host -side storage device;
- and
- carries out, upon receiving a return instruction from the host device, return processing in accordance with the sleep state information stored in the host-side storage device.
Dependencies are inferred from the claim text.