Methods and apparatus for loading firmware on demand
AssigneeApple Inc.
InventorsVladislav Petkov, Haining Zhang, Karan Sanghi, Saurabh Garg
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Abstract
Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.
Claims20
A method for initializing firmware for execution on a processor with limited access to memory, comprising:
- resetting a peripheral processor;
- establishing a physical link interface;
- initializing a secondary storage;
- loading the peripheral processor with an initial image;
- and
- causing the peripheral processor to execute the initial image.
An electronic device configured to initialize firmware for execution on a processor with limited access to memory, comprising:
- a host processor;
- a peripheral processor;
- a physical bus interface configured to couple the host processor to the peripheral processor;
- and
- a software framework configured to be executed by the host processor and the peripheral processor, the software framework comprising logic configured to:
- reset the peripheral processor through use of the host processor;
- establish a communication link between the peripheral processor and the host processor using the physical bus interface;
- initialize a secondary storage;
- load the peripheral processor with an initial image;
- and
- cause the peripheral processor to execute the initial image.
A peripheral processing device, comprising:
- a processing unit;
- a physical bus interface in communication with the processing unit, the physical bus interface coupled to a communications link;
- an array of registers that is coupled to the communications link;
- and
- a memory structure that is coupled to the communications link;
- wherein the peripheral processing device is further configured to:
- receive a reset signal from a host processor via the communications link;
- receive a portion of a firmware image from the host processor while the peripheral processing device is held in a reset condition;
- and
- execute the portion of the firmware image.
Dependencies are inferred from the claim text.