Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization

A digital data processor comprising:

• an instruction memory storing instructions each specifying a data processing operation and at least one data operand field;
• an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand;
• at least one functional unit connected said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results;
• a streaming engine connected to said instruction decoder operable in response to a first stream start instruction to recall from memory a first stream of an instruction specified sequence of a plurality of first data elements and to a second stream start instruction to recall from memory a second stream of an instruction specified sequence of a plurality of second data elements, said streaming engine including
• a first address generator for generating a first stream memory addresses corresponding to said first stream of an instruction specified sequence of a plurality of first data elements,
• a second address generator for generating a second stream memory addresses corresponding to said second stream of an instruction specified sequence of a plurality of second data elements,
• a combined arbiter and memory interface connected to said first address generator, said second address generator and the memory, said combined arbiter and memory interface comprising:
• a first arbiter connected to said first address generator for receiving a next sequential first address and a next following first address and said second address generator for receiving a next sequential second address and a next following second address, said first arbiter selecting one of said next sequential first address, said next following first address, said next sequential second address and said next following second address,
• a first memory port connected to said first arbiter and the memory for submitting a memory access request to the memory corresponding to said address selected by said first arbiter, said first memory port having memory access credits equal to a number of memory access requests that can currently be submitted to the memory,
• a second arbiter connected to said first address generator for receiving a next sequential first address and a next following first address and said second address generator for receiving a next sequential second address and a next following second address, said second arbiter selecting one of said next sequential first address, said next following first address, said next sequential second address and said next following second address,
• a second memory port connected to said second arbiter and the memory for submitting a memory access request to the memory corresponding to said address selected by said second arbiter, said second memory port having memory access credits equal to a number of memory access requests that can currently be submitted to the memory,
• an arbiter preference unit connected to said first arbiter and to said second arbiter, said arbiter preference unit selecting one of a first preference between said first address unit and said first arbiter and between said second address unit and said second arbiter and a second preference between said second address unit and said first arbiter and between said first address unit and said second arbiter,
• each of said first arbiter and said second arbiter operable to
• if the corresponding memory port has non-zero credits and if said preferred address generator generates a next sequential address, selecting said next sequential address of the preferred address generator for submission to the corresponding memory port and toggling said preference of said arbiter preference unit,
• if the corresponding memory port has non-zero credits, said preferred address generator does not generate a next sequential address, said other memory port has one credit and said non-preferred address generator generates a next sequential address, selecting said next sequential address of the non-preferred address generator for submission to the corresponding memory port and toggling said preference of said arbiter preference unit, and
• if the corresponding memory port has zero credits, said preferred address generator does not generate a next sequential address, said other memory port has at least two credits and said non-preferred address generator generates a next following address, selecting said next following address of the non-preferred address generator for submission to the corresponding memory port and toggling said preference of said arbiter preference unit,
• a first stream head register storing a first data element to be used as an operand by said at least one functional unit, and
• a second stream head register storing a second data element to be used as an operand by said at least one functional unit,
• wherein said at least one functional unit is responsive to a first stream operand instruction to receive at least one operand from said first stream head register;
• and
• wherein said at least one functional unit is responsive to a second stream operand instruction to receive at least one operand from said second stream head register.