Bandwidth reduction for instruction tracing

Abstract

Systems and methods pertain to reducing bandwidth of instruction tracing for a processor, using an Embedded Trace Macrocell (ETM). Packets, which include trace information for load/store instructions executed in the processor, are generated. A P-Header comprising commit information for load/store instructions of up to a maximum number of two or more packets is generated. The P-Header is generated for the maximum number of two or more packets if none of the load/store instructions in the maximum number of two or more packets were killed. If a load/store instruction in a packet was killed, a P-Header comprising commit information for the packet comprising the load/store instruction which was killed is generated and placed in an instruction trace immediately after that packet, even if the maximum number is not reached.

Dependencies are inferred from the claim text.