Combining loads or stores in computer processing
AssigneeQUALCOMM Incorporated
InventorsKevin JAGET, Michael William MORROW, James Norris DIEFFENDERFER
Life of this patent
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Abstract
Aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in processors. An exemplary method includes detecting a pattern of pipelined instructions to access memory using a first portion of available bus width and, in response to detecting the pattern, combining the pipelined instructions into a single instruction to access the memory using a second portion of the available bus width that is wider than the first portion. Devices including processors using disclosed aspects may execute currently available software in a more efficient manner without the software being modified.
Claims20
A method, comprising:
- detecting a pattern of pipelined instructions to access memory using a first portion of available bus width;
- and
- in response to detecting the pattern, combining the pipelined instructions into a single instruction to access the memory using a second portion of the available bus width that is wider than the first portion.
A processor, comprising:
- a pattern detection circuit configured to:
- detect a pattern of pipelined instructions to access memory using a first portion of available bus width;
- and
- in response to detecting the pattern, combine the pipelined instructions into a single instruction to access the memory using a second portion of the available bus width that is wider than the first portion.
An apparatus, comprising:
- means for detecting a pattern of pipelined instructions to access memory using a first portion of available bus width;
- and
- means for combining, in response to detecting the pattern, the instructions into a single instruction to access the memory using a second portion of the available bus width that is wider than the first portion.
Dependencies are inferred from the claim text.