Information processing apparatus

An information processing apparatus comprising:

• a host device including a volatile first memory and a first control circuit;
• a memory system including a non-volatile second memory in which user data is stored, and a second control circuit that executes transfer of the user data between the host device and the second memory;
• a first power supply circuit that starts and stops power supply to the second control circuit;
• and
• a second power supply circuit that starts and stops power supply to the second memory, wherein
• the first memory includes an area, the area being used by the second control circuit,
• the second circuit uses the area as a buffer for the transfer, and
• the first control circuit causes the first power supply circuit to start the power supply to the second control circuit and transmits an access command to the memory system, and the second control circuit, while the power supply to the second memory is stopped, processes the access command by using the buffer.