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US 2017/0249097 A1Published application
Controller and memory system
AssigneeKabushiki Kaisha Toshiba
InventorYasuyuki EGUCHI
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a controller determines a write operation, when a write request to a memory, a write address and data are received, by comparing an amount of use of a write buffer and a threshold for determining a change of a write operation to the memory. The memory is capable of overwriting first data to second data at an identical physical address of the memory. By the determined write operation, the received data is written to the received write address of the memory.
Claims14
A controller comprising:
- a host interface circuit configured to receive a write request to a memory, a write address and data;
- a determination circuit configured to determine a write operation in accordance with an amount of use of the data to be written of a write buffer, the write buffer storing the data received by the host interface circuit;
- and
- a change circuit configured to change a notification method to a host in accordance with the write operation determined by the determination circuit.
1 more element
A memory system comprising:
- a memory including write flags which are provided for respective pages and indicate that write is being executed;
- and
- a controller comprising:
- a setting circuit configured to set, when a write request to the memory, a write address and data are received, the write flag of a page corresponding to the received write address;
- and
- a reset circuit configured to write the received data to the received write address of the memory, and reset the write flag corresponding to the received write address, when the write of the received data has ended.
3 more elements
A memory system comprising:
- a memory;
- a controller comprising:
- a host interface circuit configured to receive a write request to the memory, a write address and data;
- a determination circuit configured to determine a write operation in accordance with the a length of the write request;
- and
- a write circuit configured to write the received data to the received write address of the memory in accordance with the write operation determined by the determination circuit.
3 more elements
Dependencies are inferred from the claim text.