Methods and apparatus for balancing current across parallel loads

A current-balancing circuit comprising:

• a plurality of parallel load paths electrically connected to a constant source of current, each of the plurality of parallel load paths comprising a single load or a plurality of loads connected in series;
• and
• a current mirror configured to balance the current in the plurality of parallel load paths, the current mirror comprising:
• a plurality of bipolar transistors, wherein each of the plurality of transistors is electrically connected to a respective one of the plurality of parallel load paths, wherein each of the plurality of transistors comprises a base, an emitter, and a collector, and wherein a plurality of bases of the plurality of transistors is electrically connected to create a common base node;
• a plurality of base resistors, each of the plurality of base resistors electrically connecting a collector and a base of a respective one of the plurality of transistors;
• and
• a control node, electrically connecting the plurality of base resistors, the control node configured to be driven by an average voltage of the plurality of loads.

A current-balancing circuit comprising:

• a plurality of parallel load paths electrically connected to a constant source of current, each of the plurality of parallel load paths comprising a single load or a plurality of loads connected in series;
• a current mirror configured to balance the current in the plurality of parallel load paths, the current mirror comprising:
• a plurality of bipolar transistors, wherein each of the plurality of transistors is electrically connected to a respective one of the plurality of parallel load paths,
• wherein each of the plurality of transistors comprises a base, an emitter, and a collector, and wherein a plurality of bases of the plurality of transistors is electrically connected to create a common base node;
• a plurality of base resistors, each of the plurality of base resistors electrically connecting a collector and a base of a respective one of the plurality of transistors;
• and
• a control node, electrically connecting the plurality of base resistors, the control node configured to be driven by an average voltage of the plurality of loads;
• and
• at least one processor electrically connected to each of the plurality of parallel loads, the at least one processor configured to:
• identify a threshold voltage at which performance deterioration of the plurality of transistors occurs;
• detect a voltage across the plurality of transistors;
• compare the voltage to the threshold voltage;
• and
• when the voltage is greater than the threshold voltage, reduce output of the constant source of current.