Semiconductor apparatus
AssigneeSK hynix Inc.
InventorsHyeng Ouk LEE, Yong Deok CHO
Life of this patent
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Abstract
A semiconductor apparatus includes a detection voltage generation circuit configured to generate a first detection voltage and a second detection voltage of which voltage levels are varied according to characteristics of a PMOS transistor and an NMOS transistor in response to a detection enable signal, a code generation circuit configured to generate a detection code in response to the voltage levels of the first and second detection voltages, a reference voltage generation circuit configured to generate a reference voltage in response to the detection code, an internal voltage generation circuit configured to generate an internal voltage in response to the reference voltage, and an internal circuit configured to operate by receiving the internal voltage.
Claims19
A semiconductor apparatus comprising:
- a detection voltage generation circuit configured to generate a first detection voltage and a second detection voltage of which voltage levels are varied according to characteristics of a PMOS transistor and an NMOS transistor in response to a detection enable signal;
- a code generation circuit configured to generate a detection code in response to the voltage levels of the first and second detection voltages;
- a reference voltage generation circuit configured to generate a reference voltage in response to the detection code;
- an internal voltage generation circuit configured to generate an internal voltage in response to the reference voltage;
- and
- an internal circuit configured to operate by receiving the internal voltage.
A semiconductor apparatus comprising:
- a detection voltage generation circuit configured to generate a first detection voltage of which a voltage level is varied according to a characteristic of a PMOS transistor and a second detection voltage of which a voltage level is varied according to a characteristic of an NMOS transistor;
- a code generation circuit configured to decode a P code having a code value corresponding to the voltage level of the first detection voltage and an N code having a code value corresponding to the voltage level of the second detection voltage by generating the P code and the N code and output a decoding result as a first detection code;
- an addition/subtraction circuit configured to generate a second detection code by performing an add operation or a subtract operation on an offset code and the first detection code;
- a reference voltage generation circuit configured to generate a reference voltage corresponding to a code value of the second detection code;
- an internal voltage generation circuit configured to generate an internal voltage corresponding to a voltage level of the reference voltage;
- and
- an internal circuit configured to operate by receiving the internal voltage.
Dependencies are inferred from the claim text.