Adapting scan architectures for low power operation

An integrated circuit comprising:

• (a) a first core of first functional circuits:
• (b) a first scan path circuit formed of serially connected scan cells, the first scan path circuit being coupled to the first functional circuits to carry stimulus signals to the first functional circuits and to receive response signals from the first functional circuits, the first scan path circuit having a first serial data input, a first serial data output, and first control inputs, the first scan path circuit being organized in selectable, separate first scan path parts, each scan path part having a serial input coupled to the first serial data input, a serial output coupled to the first serial data output, and a separate set of part control inputs;
• and
• (c) a second core separate from the first core and including second functional circuits;
• (ii) a second scan path circuit formed of serially connected scan cells, the second scan path circuit being coupled to the second functional circuits to carry stimulus signals to the second functional circuits and to receive response signals from the second functional circuits, the second scan path circuit having a second serial data input coupled in series with the first serial data output, a second serial data output, and second control inputs, the second scan path circuit being organized in selectable, separate second scan path parts, each scan path part having a serial input coupled to the second serial data input, a serial output coupled to the second serial data output, and a separate set of part control inputs.