Measurement system that stores pre- and post-qualification signal data

A measurement system that ensures that a preselected number of digital data samples are stored before and after a qualification signal becomes valid when the measurement system is performing a qualified store algorithm, the measurement system comprising:

• an analog-to-digital converter (ADC) configured to sample a time-varying waveform to create an acquisition record made up of acquired digital data samples;
• memory;
• and
• a processor configured to perform the qualified store algorithm when the measurement system is in a qualified storage mode of operations, wherein when the processor performs the qualified store algorithm, the processor causes N digital data samples acquired before the qualification signal became valid to be stored in a first portion of memory, causes X digital data samples acquired during a time window that starts when the qualification signal becomes valid and ends when the qualification signal becomes invalid to be stored in a second portion of memory, and causes M digital data samples acquired after the qualification signal becomes invalid to be stored in a third portion of memory, where N, X and M are integers.

A qualified store method for use in a measurement system that ensures that a preselected number of digital data samples are stored before and after a qualification signal becomes valid, the method comprising:

• sampling a time-varying waveform to create an acquisition record made up of acquired digital data samples;
• in a finite state machine (FSM), monitoring a state of a qualification signal to determine when the state of the qualification signal changes from an invalid state to a valid state and from the valid state to the invalid state;
• and
• in the FSM, entering a pre-qualification store (Store Pre-Qual) state in which acquired digital data samples are written to a first portion of memory that acts as a circular buffer, the circular buffer having N storage locations for storing N respective acquired digital data samples, where N is an integer, wherein when the FSM is in the Store Pre-Qual state and the state of the qualification signal changes from the invalid state to the valid state, the FSM exits the Store Pre-Qual state and enters a qualification store (Store Qual) state in which acquired digital data samples are written to a second portion of memory, and wherein when the FSM is in the Store Qual state and the state of the qualification signal changes from the valid state to the invalid state, the FSM exits the Store Qual state and enters a post-qualification store (Store Post-Qual) state in which acquired digital data samples are written to a third portion of memory, the third portion of memory having M digital data sample storage locations, where M is an integer.

A non-transitory computer-readable medium having computer code stored thereon for execution by at least one processor, the computer code comprising:

• a first code segment that monitors a state of a qualification signal to determine when the state of the qualification signal changes from an invalid state to a valid state and from the valid state to the invalid state;
• a second code segment that causes acquired digital data samples to be written to a first portion of memory while the qualification signal is in the invalid state, the first portion of memory acting as a circular buffer, the circular buffer having N storage locations for storing N respective acquired digital data samples, where N is an integer;
• a third code segment that causes acquired digital data samples to be written to a second portion of memory when the qualification signal changes from the invalid state to the valid state and to continue writing acquired digital data samples to the second portion of memory until the qualification signal changes from the valid state to the invalid state;
• and
• a fourth code segment that causes acquired digital data samples to be written to a third portion of memory when the qualification signal changes from the valid state to the invalid state and to continue writing acquired digital data samples to the third portion of memory until either M acquired digital data samples have been written to the third portion of memory or the qualification signal changes from the invalid state to the valid state, where M is an integer.