Systems, apparatuses, and methods for performing a double blocked sum of absolute differences
AssigneeIntel Corporation
InventorsELMOUSTAPHA OULD-AHMED-VALL, MOSTAFA HAGOG, ROBERT VALENTINE, AMIT GRADSTEIN, SIMON RUBANOVICH, ZEEV SPERBER
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Abstract
Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.
Claims20
A method of performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode, the method comprising steps of:
- executing the single vector double block packed sum of absolute differences instruction to, on a per data lane basis, compute a SAD of selected quadruplets of data elements of the first and second sources;
- and
- storing each calculated SAD into the destination vector register.
An article of manufacture comprising:
- a tangible machine-readable storage medium having stored thereon an occurrence of an instruction, wherein the instruction's format specifies as its source operands a first and second source and an immediate and specifies as its destination a single destination vector register, and wherein the instruction format includes an opcode which instructs a machine, responsive to the single occurrence of the single instruction, to cause on a per data lane basis, a computation of a SAD of selected quadruplets of data elements of the first and second sources and storage of each calculated SAD into the destination vector register.
An apparatus comprising;
- a hardware decoder to decode a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode;
- execution logic to, on a per data lane basis, compute a SAD of selected quadruplets of data elements of the first and second sources and store each calculated SAD into the destination vector register.
Dependencies are inferred from the claim text.