Dut continuity test with only digital io structures apparatus and methods associated thereof

A method for identifying open circuits by measuring RC delays on a DUT TO comprising:

• providing a test setup comprising a tester coupled to a DUT board;
• ensuring said tester is coupled to said DUT board without a DUT;
• placing all tester pins on said tester in a high impedance state;
• configuring a first tester I/O pin connected to a DUT TO pin as tester output driving logic high;
• wherein said configuring step further comprises configuring said first tester I/O pin in a high impedance state for shortest increment possible;
• configuring said first tester I/O pin as a tester input sampling a highest reliable sample rate and recording a first sample count associated with said test setup without a DUT;
• continually sampling said first tester I/O pin during said configuring steps until a logic low is recorded;
• recording said first sample count in a non-transitory computer storage readable medium;
• saving said first sample count in said non-transitory computer storage readable medium for use in future comparison when logic low is recorded;
• repeating said placing, configuring, recording, and saving steps until all tester I/O pins connected to said DUT I/O pin have been characterized and sample counts saved;
• inserting a DUT into said test setup;
• repeating said placing, configuring, recording, and saving steps generating a second sample count associated with said DUT that is inserted into said test setup;
• and
• comparing said first sample count and said second sample count to determine if the presence of said DUT in said DUT board has created an affected sample count;
• wherein said affected sample count comprises a difference between said first sample count and said second sample count.

A method of identifying short circuits by forcing voltage on a single pin comprising:

• inserting a DUT into a test setup comprising a tester and a DUT board;
• configuring all tester I/O pins as tester output driving logic low to discharge all pins;
• placing all tester I/O pins on said tester in a high impedance state;
• configuring a first tester I/O pin connected to a first DUT I/O pin as tester output driving logic high;
• configuring a next adjacent tester I/O pin as a tester input sampling at a highest reliable sample rate generating a value of pin driven high and pin sampled;
• recording said value in a non-transitory computer storage readable medium;
• repeating said configuring and recording steps for each adjacent tester I/O pin;
• and
• repeating said configuring, recording, and repeating steps until all tester I/O pins connected to DUT I/O pins have been characterized and data recorded in said non-transitory computer storage readable medium.

A test system operable to determine a short, open, or electrical connections digitally in a device under test (DUT) continuity test, comprising:

• a first, second and third section configured to respectively apply a first, second and third test in a first sequence on at least one input and output (IO) section of a DUT and determine if at least one IO has a short, open or electrical connection;
• wherein said first section is configured for identifying one or more said open circuit by applying a plurality of first inputs on and measuring resistance-capacitance (RC) delay on said at least one TO;
• wherein said second section is configured for identifying one or more said open circuits using time domain reflectometry (TDR) on the at least one IO section;
• wherein said third section is configured for identifying one or more said short circuits by forcing voltage on a plurality of said IO sections of said DUT while measuring voltage on remaining pins to determine if said voltage is above or below a predetermined threshold associated with at least one logic value.

A method for identifying open and short circuits in at least a device under test (DUT) by a combination of testing methods comprising:

• providing a test setup comprising an electrical signal tester coupled to a DUT testing interface board;
• executing at least two of a plurality of said testing methods on said DUT including forcing voltage, measuring resistance/capacitance (RC) delays, and time domain reflectometry (TDR) with respect to said DUT;
• wherein said forcing voltage testing operations on said DUT comprises:
• ensuring said electrical signal tester is coupled to said DUT board without a DUT;
• placing all tester pins on said electrical signal tester in a high impedance state;
• performing a first plurality of configuring steps comprising configuring a first tester I/O pin connected to one or more DUT IO pin as tester output driving logic high;
• wherein said first plurality of configuring steps comprises configuring said first tester I/O pin in a high impedance state for shortest increment possible;
• configuring said first tester I/O pin as a first tester input sampling a highest reliable sample rate and recording a first sample count associated with said DUT testing interface board without said DUT installed;
• continually sampling said first tester I/O pin during said configuring steps until a logic low is recorded;
• recording said first sample count in a non-transitory computer storage readable medium;
• saving said first sample count in said non-transitory computer storage readable medium for use in future comparison when logic low is recorded;
• repeating said placing, configuring, recording, and saving steps until all tester I/O pins connected to said DUT I/O pin have been characterized and sample counts saved;
• inserting said DUT into said DUT testing interface board;
• repeating said placing, configuring, recording, and saving steps generating a second sample count associated with said DUT that is inserted into said DUT testing interface board;
• and
• comparing said first sample count and said second sample count to determine if the presence of said DUT in said DUT testing interface board has created an affected sample count;
• wherein said affected sample count comprises a difference between said first sample count and said second sample count.
• wherein said measuring resistance/capacitance (RC) delays method comprises:
• executing an RC delay sampling process comprising placing all said tester pins on said electrical signal tester in a high impedance state, configuring said first tester I/O pin connected to said first DUT I/O pin as a second tester output driving logic high, configuring said first tester I/O pin as a tester output logic low to introduce a negative edge signal, configuring said first tester I/O pin in a high impedance state, configuring said first tester I/O pin as tester input sampling a highest reliable sample rate generating a first plurality of RC delay method sample counts, recording said first plurality of RC delay method sample counts in said non-transitory computer storage readable medium, and continually sampling said first tester I/O pin during prior two configuring and recording steps at highest reliable sample rate for up to a predetermined time for reflection to propagate from said tester to said DUT and back to said electrical signal tester, wherein said RC delay related sampling steps are based on detecting an increased voltage after time zero to generate at least in part generation of said first plurality of RC delay related sample values;
• storing additional said first plurality of RC delay related sample values into said non-transitory computer storage readable medium;
• repeating said RC delay sampling steps comprising configuring, sampling, and storing steps until all tester I/O pins connected to DUT I/O pins have been characterized and additional said first plurality of RC delay related sample values for each separate DUT I/O pins stored in said non-transitory computer storage readable medium;
• repeating said RC delay sampling steps comprising configuring, sampling, storing and prior repeating steps a predetermined number of times to determine a range of respective RC delay related sample values for each tester I/O and DUT I/O pin pair which represents an open circuit between said tester I/O and DUT I/O pin pair;
• inserting said DUT into a DUT socket of said testing interface board;
• repeating said RC delay sampling steps comprising configuring, sampling and storing steps generating a second plurality of RC delay related sample values for each tester I/O and DUT I/O pin pair;
• comparing said second plurality of RC delay related values with respective said first plurality of RC delay related sample values to determine if insertion of said DUT into said testing interface board has changed a recorded pattern of at least one of said second RC delay related sample value for each tester I/O and DUT I/O pin pair.
• wherein said time domain reflectometry (TDR) method comprises using said electrical signal tester to determine if a circuit associated with said DUT I/O pin pairs exhibit an open circuit indication based on one or more first category measured values obtained based on TDR associated with at least one of said DUT I/O pin pairs