Modified tunneling field effect transistors and fabrication methods
AssigneeGlobalfoundries Inc.
InventorsYanxiang LIU, Min-hwa CHI
Life of this patent
Estimating the term…
Abstract
Tunneling field effect transistors and fabrication methods thereof are provided, which include: an integrated circuit device which includes a circuit input configured to receive an input voltage and a circuit output configured to deliver an output current. The integrated circuit also includes a circuit element having at least one tunneling field effect transistor (TFET). The circuit element connects the circuit input to the circuit output and is characterized by a V-shaped current-voltage diagram. The V-shaped current-voltage diagram describes the relationship between the input voltage of the circuit input and the output current of the circuit output.
Claims20
An integrated circuit device comprising:
- a circuit input configured to receive an input voltage;
- a circuit output configured to deliver an output current;
- and
- a circuit element comprising at least one tunneling field effect transistor (TFET), the circuit element connecting the circuit input to the circuit output and being characterized by a V-shaped current-voltage diagram, the V-shaped current-voltage diagram describing the relationship between the input voltage of the circuit input and the output current of the circuit output.
A tunneling field effect transistor (TFET), comprising:
- a gate disposed over a substrate structure;
- a source region disposed within the substrate structure, the source region being one of an n-type and a p-type;
- a drain region disposed within the substrate structure, the drain region being the other of the n-type and the p-type;
- a channel region disposed within the substrate structure between the source and drain regions, the channel region underlying, at least partially, the gate;
- a source region junction defined by an overlap of the source region with the gate wherein tunneling of one of an n-type and a p-type charge carrier occurs;
- and
- a drain region junction defined by an overlap of the drain region with the gate wherein tunneling of the other of the n-type and the p-type charge carrier occurs;
- wherein the tunneling of the n-type and p-type charge carriers is characterized by a V-shaped current-voltage diagram of the TFET.
Dependencies are inferred from the claim text.