Semiconductor memory device
AssigneeRenesas Electronics Corporation
InventorToshihiko FUNAKI
Life of this patent
Estimating the term…
Abstract
A stack memory includes a base chip, a memory chip stacked over the base chip, and a via 42 provided between the base chip and the memory chip. The base chip has an external interface circuit and a late write control circuit. The external interface circuit externally receives/transmits write data and read data. The late write control circuit has at least a register storing write data externally supplied through the external interface circuit. The memory chip has a memory cell array and a late write control circuit having at least a register storing write data supplied from the register through the via.
Claims10
A semiconductor memory device comprising:
- a base chip;
- a first memory chip which is stacked over the base chip;
- and
- a first through via which is provided between the base chip and the first memory chip, and is used for transmitting read data and write data;
- and
- wherein the base chip has
- an external interface circuit which externally receives/transmits write data and read data, and
- a first late write control circuit which has at least a first register storing write data supplied externally through the external interface circuit, and
- wherein the first memory chip has
- a memory cell array which has a plurality of memory cells arranged in matrix, and
- a second late write control circuit which has at least a second register storing write data supplied from the first register through the first through via, and writes write data output from the second register into a target memory cell for writing.
The semiconductor memory device according to claim. 1, further comprising
- a second memory chip which is stacked over the base chip, and
- wherein the first and second memory chips include a plurality of memory banks of a same channel, formed of the memory cell array and the second late write control circuit.
The semiconductor memory device according to claim. 7, further comprising
- a gating circuit which stops supplying the address signal for data reading to the memory cell array, when there is coincidence between an address signal corresponding to write data stored in the first register and an externally supplied address signal for data reading.
Dependencies are inferred from the claim text.