Flexible Polynomial-Based Interleaver

A method, comprising:

• receiving, by one or more processing elements:
• input data samples;
• a plurality of polynomial coefficients that include coefficients for at least a third-order polynomial;
• a start index;
• and
• information indicating a window size for non-sequential traversal of interleaver indices;
• generating, by address circuitry, bank and address information for writing the input data samples to ones of a plurality of memory blocks in parallel, wherein the generating is based on:
• an order of the polynomial, a code block length, the start index, and the information indicating the window size;
• storing, by the plurality of memory blocks, interleaved input data samples in parallel based on the bank and address information;
• and
• outputting, by output circuitry, interleaved data samples from the plurality of memory blocks.

A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware circuit in a format recognized by a computing system configured to use the design information to implement the circuit according to the design, including:

• a plurality of memory blocks configured to store interleaved input data samples in parallel;
• one or more circuit elements configured to:
• receive input data samples, a plurality of polynomial coefficients, a start index, and information indicating a window size for non-sequential traversal of interleaver indices, wherein the plurality of polynomial coefficients includes coefficients for at least a third-order polynomial;
• and
• generate interleaved bank and address information for writing the input data samples to the plurality of memory blocks, based on an order of the polynomial, a code block length, the start index, and the information indicating the window size;
• and
• output circuitry configured to provide interleaved data samples from the plurality of memory blocks.