Network logic synthesis
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
InventorsChi-Chuan CHUANG, Yi-Hsiang LAI, Jie-Hong CHIANG
Life of this patent
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Abstract
A system comprises at least one processor configured to perform technology mapping to map logic elements in a logic netlist to corresponding dual-rail modules in a library. The technology mapping results in a network of interconnected nodes and the mapped dual-rail modules are arranged at corresponding nodes of the network. The processor is configured to optimize the network and perform the technology mapping based on at least one satisfiability-don't-care condition. Performance analysis may be performed by calculating a cycle time of a pipeline node in the network based on a calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.
Claims20
A system, comprising at least one processor configured to perform:
- technology mapping to map logic elements in a logic netlist to corresponding dual-rail modules in a library, the technology mapping resulting in a network of interconnected nodes, the mapped dual-rail modules arranged at corresponding nodes of the network;
- and
- an optimization of the network,
- wherein the at least one processor is configured to perform the technology mapping based on at least one satisfiability-don't-care (SDC) condition.
A computer program product, comprising a non-transitory, computer-readable medium containing instructions therein which, when executed by at least one processor, cause the at least one processor to perform:
- a performance analysis of a network of interconnected nodes, the nodes configured to perform corresponding logic functions, wherein the performance analysis comprises, for a pipeline node in the network:
- calculating a pre-charging finish time of the pipeline node based on an evaluation finish time of a fanout node of the pipeline node and an acknowledge output time parameter of the fanout node, and
- calculating a cycle time of the pipeline node based on the calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.
A system comprising at least one processor configured to:
- map logic elements in a logic netlist to corresponding dual-rail modules in a library, the mapping of the logic elements resulting in a network of interconnected nodes and dual-rail modules arranged at corresponding nodes of the network;
- optimize the network;
- and
- slack match a pipeline in the optimized network.
Dependencies are inferred from the claim text.