Generation of Linear Feedback Shift Register Based Pseudo Random Noise (PRN) Spreading Code Sequence for Global Navigation Satellite System
AssigneeThe Boeing Company
InventorsPhilip L. Wei, Abraham Hwang, Nigel Chen
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Abstract
Technology to generation of linear feedback shift register based PRN spreading code sequence using a processor device in a computing system is disclosed. A system is provided for generating a GNSS code sequence in a computer system, the system comprising one or more logic circuits configured to at least: receive a plurality of waveform generation parameters; select between a short pseudo-random noise (PRN) cycle and a long PRN cycle according to at least one of the plurality of waveform generation parameters; and emulate a plurality of linear feedback shift registers (LFSR) for generating a block of PRN code chips.
Claims20
A system for generating a Global Navigation Satellite System (GNSS) code sequence in a computer system, the system comprising one or more logic circuits configured to at least:
- receive a plurality of waveform generation parameters;
- select between a short pseudo-random noise (PRN) cycle and a long PRN cycle according to at least one of the plurality of waveform generation parameters;
- and
- emulate a plurality of linear feedback shift registers (LFSR) for generating a block of PRN code chips.
A method of generating a Global Navigation Satellite System (GNSS) code sequence in a computer system, the method comprising:
- receiving a plurality of waveform generation parameters;
- selecting between a short pseudo-random noise (PRN) cycle and a long PRN cycle according to at least one of the plurality of waveform generation parameters;
- and
- emulating a plurality of linear feedback shift registers (LFSR) for generating a block of PRN code chips.
A method of providing security in a computer system, the method comprising:
- receiving a plurality of waveform generation parameters;
- selecting between a short pseudo-random noise (PRN) code sequence cycle and a long PRN code sequence cycle according to at least one of the plurality of waveform generation parameters;
- and
- emulating a plurality of linear feedback shift registers (LFSR) for generating a block of PRN code chips by iteratively generating an output bit for a PRN code sequence using an LFSR table and zero filling a PRN code sequence bit up to a determined chip block size.
Dependencies are inferred from the claim text.