Heterojunction field-effect transistor

Process for fabricating a heterojunction field-effect transistor comprising a semiconductor structure made up of superposed layers, comprising:

• a) providing on a substrate layer (1):
• a buffer layer (2) composed of a semiconductor material having a hexagonal crystal structure, namely Ga(1-x-y)Al(x)In(y)N, where x and y are comprised between 0 inclusive and 1 inclusive, the sum x+y being lower than or equal to 1;
• a channel layer (3) on the buffer layer, this channel layer being composed of a material having a hexagonal crystal structure, namely Ga(1-z-w)Al(z)In(w)N, where z and w may be comprised between 0 inclusive and 1 inclusive, the sum z+w being lower than or equal to 1, at least one of z and w being different from x or y, respectively;
• and
• a barrier layer (4) on this channel layer, this barrier layer being composed of a material having a hexagonal crystal structure, namely Ga(1-z′-w′)Al(z′)In(w′)N, where z′ and w′ may be comprised between 0 inclusive and 1 inclusive, the sum z′+w′ being lower than or equal to 1, at least one of z′ and w′ being different from z or w, respectively;
• b) depositing a dielectric masking layer (5) on the barrier layer;
• c) forming an opening in the dielectric masking layer;
• d) growing by high-temperature epitaxy a semiconductor material (6, 6′) having a hexagonal crystal structure, namely Ga(1-x′-y′)Al(x′)In(y′)N, doped with germanium, where x′ and y′ are comprised between 0 inclusive and 1 inclusive, the sum x′+y′ being lower than or equal to 1, on a growth zone defined by the opening formed in the masking layer;
• e) depositing a source or drain contact electrode (15, 16) on the material thus deposited by epitaxy in step d);
• and
• f) depositing a gate electrode (13) in a location outside of the growth zone.