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US 2017/0069660 A1Published application
Cell structure in intergrated circuits for eco at upper metal layer and method for forming spare cell structure
AssigneeSamsung Electronics Co., Ltd.
InventorHyun-Teck OH
Life of this patent
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Abstract
An integrated circuit includes a functional cell, and a spare gate cell configured to change or add a function of the functional cell in response to an engineering change order (ECO). The spare gate cell includes transistors configured as a decoupling capacitor before the ECO, and the spare gate cell is configured to change into an ECO cell including an interconnection metal line pattern disposed in the decoupling capacitor after the ECO.
Claims20
An integrated circuit comprising:
- a functional cell;
- and
- a spare gate cell configured to change or add a function of the functional cell in response to an engineering change order (ECO),
- wherein the spare gate cell comprises transistors configured as a decoupling capacitor before the ECO, and
- wherein the spare gate cell is configured to change into an ECO cell comprising an interconnection metal line pattern disposed in the decoupling capacitor after the ECO.
2 more elements
A method for forming a spare cell structure of an integrated circuit, the method comprising:
- forming, in the integrated circuit, a spare gate cell as a decoupling capacitor before an engineering change order (ECO);
- and
- forming an interconnection metal line pattern in the decoupling capacitor after the ECO event to change the spare gate cell into an ECO cell.
An integrated circuit comprising:
- a functional cell;
- and
- a spare gate cell configured to change or add a function of the functional cell in response to an engineering change order (ECO),
- wherein before the ECO, the spare gate cell comprises:
- first transistors having a first conductivity type;
- second transistors having a second conductivity type;
- a first interconnection line connected to a source or a drain of each of two or more of the first transistors;
- a second interconnection line connected to a source or a drain of each of two or more of the second transistors;
- and
- a third interconnection line connected to gates of the first group transistors and the second group transistors, and
- wherein after the ECO, the spare gate cell further comprises a fourth interconnection line connected to the first interconnection line and the second interconnection line.
8 more elements
Dependencies are inferred from the claim text.