Shift register and driving method thereof, gate driving device, display panel

A shift register comprising a plurality of cascaded shift register elements, wherein each shift register element comprises:

• an input module (201) configured to provide a first DC voltage signal (VDS) to a pull-up node as the output of the input module in response to an input signal (INPUT) of an input signal terminal;
• an output module (202) configured to provide a clock signal (CLK) to an output terminal of the shift register element in response to a voltage signal outputted by the pull-up node;
• a reset module (203) configured to provide a second DC voltage signal (VSD) to the pull-up node in response to a reset signal (RESET), wherein the second DC voltage signal is at a low level when the first DC voltage signal is at a high level, and is at a high level when the first DC voltage signal is at a low level;
• a first pull-down module (204) configured to provide the second DC voltage signal (VSD) or the first DC voltage signal (VDS) respectively to the pull-down node as the output of the first pull-down module in response to the input signal (INPUT) of the input signal terminal or to the reset signal;
• and
• a second pull-down module (205) configured to provide a power supply anode voltage signal (VDD) to the pull-down node and provide a power supply cathode voltage signal (VSS) outputted by a power supply cathode to the output terminal in response to a voltage signal of the pull-down node.

A gate driving device, wherein the shift register comprises a plurality of cascaded shift register elements, each shift register element comprising:

• an input module (201) configured to provide a first DC voltage signal (VDS) to a pull-up node as the output of the input module in response to an input signal (INPUT) of an input signal terminal;
• an output module (202) configured to provide a clock signal (CLK) to an output terminal of the shift register element in response to a voltage signal outputted by the pull-up node;
• a reset module (203) configured to provide a second DC voltage signal (VSD) to the pull-up node in response to a reset signal (RESET), wherein the second DC voltage signal is at a low level when the first DC voltage signal is at a high level, and is at a high level when the first DC voltage signal is at a low level;
• a first pull-down module (204) configured to provide the second DC voltage signal (VSD) or the first DC voltage signal (VDS) respectively to the pull-down node as the output of the first pull-down module in response to the input signal (INPUT) of the input signal terminal or to the reset signal;
• and
• a second pull-down module (205) configured to provide a power supply anode voltage signal (VDD) to the pull-down node and provide a power supply cathode voltage signal (VSS) outputted by a power supply cathode to the output terminal in response to a voltage signal of the pull-down node.

A display panel comprising a gate driving device, wherein the gate driving device comprises a shift register and the shift register comprises a plurality of cascaded shift register elements, each shift register element comprising:

• an input module (201) configured to provide a first DC voltage signal (VDS) to a pull-up node as the output of the input module in response to an input signal (INPUT) of an input signal terminal;
• an output module (202) configured to provide a clock signal (CLK) to an output terminal of the shift register element in response to a voltage signal outputted by the pull-up node;
• a reset module (203) configured to provide a second DC voltage signal (VSD) to the pull-up node in response to a reset signal (RESET), wherein the second DC voltage signal is at a low level when the first DC voltage signal is at a high level, and is at a high level when the first DC voltage signal is at a low level;
• a first pull-down module (204) configured to provide the second DC voltage signal (VSD) or the first DC voltage signal (VDS) respectively to the pull-down node as the output of the first pull-down module in response to the input signal (INPUT) of the input signal terminal or to the reset signal;
• and
• a second pull-down module (205) configured to provide a power supply anode voltage signal (VDD) to the pull-down node and provide a power supply cathode voltage signal (VS S) outputted by a power supply cathode to the output terminal in response to a voltage signal of the pull-down node.