Structure for interconnect parasitic extraction

Abstract

A structure for extracting interconnect parasitic in a ring oscillator is disclosed. The ring oscillator comprises multiple logical units connected in head to tail series. The structure comprises parasitic resistance sub-structures and/or parasitic capacitance sub-structures each connected to a corresponding logical unit. The structure can be used to determine errors in extracting parasitic resistance of polysilicon interconnects and metal interconnects, and/or errors in extracting parasitic capacitance between the polysilicon interconnects and between the metal interconnects. Therefore, the parasitic extraction error can be calibrated accordingly to obtain more precise circuit simulation results and more accurate device model and BEOL model.

Dependencies are inferred from the claim text.