Time and cell de-interleaving circuit and method for performing time and cell de-interleaving
AssigneeMStar Semiconductor, Inc.
InventorChun-Chieh Wang
Life of this patent
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AssigneeMStar Semiconductor, Inc.
InventorChun-Chieh Wang
Estimating the term…
A method for performing time and cell de-interleaving on an interleaved signal including a plurality of cells is provided. The method includes: providing a first memory for storing the cells, the first memory written and read each time in a unit of one cell group, the cell group including K cells, where K is a positive integer greater than 1; providing a second memory for storing the cells read from the first memory; reading the cells from the first memory, and writing the cells to the second memory according to a writing rule of a plurality of permutation rules, K consecutive cells written to the second memory being from the same cell group; and reading the cells from the second memory according to a reading rule of the permutation rules, to cause the cells read from the second memory to be complete with time de-interleaving and cell de-interleaving.
A time and cell de-interleaving circuit, located at a signal receiver of a communications system, performing time de-interleaving and cell de-interleaving on an interleaved signal, the interleaved signal comprising a plurality of cells, the time and cell de-interleaving circuit comprising:
A method, applied to a signal receiver of a communication system, for performing time and cell de-interleaving on an interleaved signal, the interleaved signal comprising a plurality of cells, the method comprising:
A time and cell de-interleaving circuit, located in a signal receiver of a communication system, performing time de-interleaving and cell de-interleaving on an interleaved signal, the interleaved signal comprising a plurality of cells, the time and cell de-interleaving circuit comprising:
Dependencies are inferred from the claim text.