Quadrature demodulator for a very high bit rate rfid receiver

A quadrature demodulation method for demodulating a received signal modulated at a carrier frequency f=1/T, wherein, from a signal locked at this frequency, a first square logic signal (g+(t)) at the frequency 2f and a second square logic signal (g+(t)) being inverse from the first one are generated and there are performed:

• a first integration of a first component of the received signal (y(t), y+(t)) when the first logic signal is in a high state, a first integration result being obtained when the first logic signal is in a low state;
• a second integration of said component of the received signal (y(t), y+(t)) when the second logic signal is in a high state, a second integration result being obtained when the second logic signal is in a low state;
• a subtraction for subtracting the second integration result from the first integration result and providing samples zn at the frequency 4f;
• a first combination for combining successive samples zn, zn-1, zn-2, zn-3 and providing samples In=zn−zn-1−zn-2+zn-3 at the frequency 4f;
• a second combination for combining successive samples zn, zn-1, zn-2, zn-3 and providing samples Qn=−zn−zn-1+zn-2+zn-3 at the frequency 4f;
• a first decimation for decimating the samples In with a decimation factor 4 for providing in-phase component samples I(kT);
• a second decimation for decimating the samples Qn with a decimation factor 4 for providing quadrature component samples Q(kT).