A decoding apparatus according to the preceding claim, said apparatus being configured for implementing check node operations by means of L processing units configured dynamically to compute Rni(j), with i=1, . . . , L, each one of the L processing units share 3×dc inputs that correspond to the symbols Qn1(j),Qn2(j) and to the coefficients of the code, said inputs of each processing unit are combined by means of 2×dc GF multipliers and 2×dc GF adders, said processing units including all the logic necessary to compute L different syndromes as an intermediate step and a variable number of pipeline stages that may vary from 0 to log 2(dc)+2 depending on the speed of said processing unit.