Gain calibration for adc with external reference

An analog-to-digital converter (ADC), comprising:

• a passive sample and hold (SH) capacitance arranged to receive an analog input voltage;
• a digital-to-analog converter (DAC) capacitance comprising an array of multiple switched capacitances, coupled to the SH capacitance at a first node and switchably coupled to a reference voltage at another node of the DAC;
• a comparator coupled at the first node at an input of the comparator
• a successive approximation register (SAR) coupled to an output of the comparator, an output of the SAR comprising a digital output of the ADC;
• a calibration capacitance coupled at the first node, the calibration capacitance adjustable to minimize a difference between a capacitance value of the SH capacitance and a capacitance value comprising a sum of the calibration capacitance and the DAC capacitance;
• and
• a calibration logic module configured to:
• couple the SH capacitance to the reference voltage at another node of the SH capacitance;
• couple the first node to a bias voltage;
• couple the DAC capacitance to ground at the other node of the DAC capacitance;
• disconnect the SH capacitance from the reference voltage and the DAC capacitance from ground and setting the first node to a high impedance state after charging the SH capacitance with the reference voltage;
• couple the SH capacitance to ground at the other node of the SH capacitance;
• couple the DAC capacitance to the reference voltage at the other node of the DAC capacitance;
• compare an injected voltage from the SH capacitance to an injected voltage from the DAC capacitance at the first node;
• place the comparator coupled to the first node on a trip point of the comparator when the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance are equal;
• and
• detect a sign of a voltage magnitude deviation between the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance, and add or subtract a capacitance from the calibration capacitance when the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance are not equal

A method, comprising:

• forming an analog-to-digital converter (ADC), including:
• coupling a passive sample and hold (SH) capacitance to a digital-to-analog converter (DAC) capacitance at a first node;
• coupling the SH capacitance to an input voltage of the ADC at another node of the SH capacitance;
• and
• coupling the DAC capacitance to a reference voltage at another node of the DAC capacitance;
• coupling a calibration capacitance at the first node;
• comparing an injected voltage from the SH capacitance to an injected voltage from the DAC capacitance at the first node;
• and
• adjusting the calibration capacitance such that a sum of the DAC capacitance and the calibration capacitance is equal to the SH capacitance;
• and
• determining a gain error cancellation weight using a calibration routine, comprising:
• coupling the SH capacitance to the reference voltage at the other node of the SH capacitance;
• coupling the first node to a bias voltage;
• coupling the DAC capacitance to ground at the other node of the DAC capacitance;
• disconnecting the SH capacitance from the reference voltage and the DAC capacitance from ground and setting the first node to a high impedance state after charging the SH capacitance with the reference voltage;
• coupling the SH capacitance to ground at the other node of the SH capacitance;
• coupling the DAC capacitance to the reference voltage at the other node of the DAC capacitance;
• comparing an injected voltage from the SH capacitance to an injected voltage from the DAC capacitance at the first node;
• placing a comparator coupled to the first node on a trip point of the comparator when the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance are equal;
• and
• detecting a sign of a voltage magnitude deviation between the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance, and adding or subtracting a capacitance from the calibration capacitance when the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance are not equal.

An analog-to-digital converter (ADC), comprising:

• a passive sample and hold (SH) capacitance arranged to receive an analog input voltage;
• a digital-to-analog converter (DAC) capacitance coupled to the SH capacitance at a first node and switchably coupled to a reference voltage at another node of the DAC;
• a calibration capacitance coupled at the first node, the calibration capacitance adjustable to track the DAC capacitance;
• and
• a calibration logic module configured to:
• couple the SH capacitance to the reference voltage at another node of the SH capacitance;
• couple the first node to a bias voltage;
• couple the DAC capacitance to ground at the other node of the DAC capacitance;
• disconnect the SH capacitance from the reference voltage and the DAC capacitance from ground and setting the first node to a high impedance state after charging the SH capacitance with the reference voltage;
• couple the SH capacitance to ground at the other node of the SH capacitance;
• couple the DAC capacitance to the reference voltage at the other node of the DAC capacitance;
• compare an injected voltage from the SH capacitance to an injected voltage from the DAC capacitance at the first node;
• place a comparator coupled to the first node on a trip point of the comparator when the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance are equal;
• and
• detect a sign of a voltage magnitude deviation between the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance, and add or subtract a capacitance from the calibration capacitance when the injected voltage from the SH capacitance and the injected voltage from the DAC capacitance are not equal.