Level converter circuit

A level conversion circuit comprising:

• a first P-ch transistor and a first N-ch transistor connected in series between a first power source and a second power source whose voltage is lower than the voltage of the first power source;
• a second P-ch transistor and a second N-ch transistor connected in series between the first power source and the second power source;
• a third P-ch transistor connected between the gate of the second P-ch transistor and the drain of the first P-ch transistor;
• a fourth P-ch transistor connected between the gate of the first P-ch transistor and the drain of the second P-ch transistor;
• a fifth P-ch transistor connected between the gate of the second P-ch transistor and a third power source;
• and
• a sixth P-ch transistor connected between the gate of the first P-ch transistor and the third power source, wherein
• differential input signals are applied to the gates of the first N-ch transistor and the second N-ch transistor,
• a bias voltage is applied to the gates of the third P-ch transistor and the fourth P-ch transistor,
• the gate of the fifth P-ch transistor is connected to a connection node of the first P-ch transistor and the first N-ch transistor, and
• the gate of the sixth P-ch transistor is connected to a connection node of the second P-ch transistor and the second N-ch transistor.