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US 2017/0012611 A1Published application
Double sampling state retention flip-flop
AssigneeNXP B.V.
InventorsJuan Echeverri Escobar, Jose de Jesus Pineda de Gyvez, Sebastien Antonius Josephus Fabrie
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Abstract
Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.
Claims20
A flip-flop circuit, the flip-flop circuit comprising:
- a master latch;
- a slave latch connected to the master latch;
- a dual-function circuit connected to the master latch and the slave latch and configured to perform state retention and double sampling;
- a control circuit configured to generate a plurality of control signals for the flip-flop circuit based on a clock signal and a delayed version of the clock signal;
- and
- an error logic circuit configured to generate an error signal based on signals from the master latch, the dual-function circuit, and the control circuit.
3 more elements
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A flip-flop circuit, the flip-flop circuit comprising:
- a master latch;
- a slave latch connected to the master latch;
- a dual-function circuit connected to the master latch and the slave latch and configured to perform state retention and double sampling;
- a plurality of switch circuits connected to an input terminal of the flip-flop circuit, to the master latch, to the slave latch, and to the dual-function circuit;
- a control circuit configured to generate a plurality of control signals for the switch circuits based on a clock signal and a delayed version of the clock signal;
- and
- an error logic circuit configured to generate an error signal based on signals from the master latch, the dual-function circuit, and the control circuit.
4 more elements
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A method for operating a flip-flop circuit, the method comprising:
- performing double-sampling using a dual-function circuit of the flip-flop circuit;
- performing state retention using the dual-function circuit of the flip-flop circuit;
- generating a plurality of control signals for the flip-flop circuit based on a clock signal and a delayed version of the clock signal using a control circuit of the flip-flop circuit;
- and
- generating an error signal based on signals from a master latch of the flip-flop circuit, the dual-function circuit, and the control circuit.
2 more elements
Dependencies are inferred from the claim text.