Two-Port SRAM Connection Structure

A static random access memory (SRAM) device comprising:

• a peripheral logic circuit;
• a first sub array and a second sub array, the first and second sub arrays each comprising:
• a plurality of two-port SRAM cells, each two-port SRAM cell comprising:
• a write port portion including a first plurality of transistors;
• and
• a read port portion including a second plurality of transistors;
• a first plurality of metal lines including a write bit line, an inverse write bit line, a read bit line, a write word line landing pad, and a read word line landing pad, wherein the first plurality of metal lines is located in a first metal layer;
• a second plurality of metal lines including a write word line, wherein the second plurality of metal lines is located in a second metal layer;
• and
• a third plurality of metal lines including a global write bit line and an inverse global write bit line, wherein the third plurality of metal lines is located in a third metal layer;
• wherein the write bit line, the inverse write bit line, the global write bit line, and the inverse global write bit line each have a routing length across the first and second sub arrays, and
• wherein the read bit line of the first sub array and the read bit line of the second sub array are physically isolated;
• and
• a plurality of jumper structures, each jumper structure comprising:
• a first metal landing pad located in the second metal layer and electrically connected to the write bit line and to the global write bit line;
• a second metal landing pad located in the second metal layer and electrically connected to the inverse write bit line and the inverse global write bit line;
• and
• a third metal landing pad located in the second metal layer and electrically connected to the read bit line and a peripheral metal line of the peripheral logic circuit, the peripheral metal line located in the first metal layer.

A static random access memory (SRAM) device comprising:

• a peripheral logic circuit;
• a first sub array and a second sub array, the first and second sub arrays each comprising:
• a plurality of two-port SRAM cells, each two-port SRAM cell comprising:
• a write port portion including a first plurality of transistors;
• and
• a read port portion including a second plurality of transistors;
• a first plurality of metal lines including a write bit line, an inverse write bit line, a read bit line, a write word line landing pad, and a read word line landing pad, wherein the first plurality of metal lines is located in a first metal layer;
• a second plurality of metal lines including a write word line, wherein the second plurality of metal lines is located in a second metal layer;
• and
• a third plurality of metal lines including a global write bit line, an inverse global write bit line, and a global read bit line, wherein the third plurality of metal lines is located in a third metal layer,
• wherein the write bit line, the inverse write bit line, the global write bit line, the inverse global write bit line, and the global read bit line each have a routing length across the first and second sub arrays, and
• wherein the read bit line of the first sub array and the read bit line of the second sub array are physically isolated;
• and
• a plurality of jumper structures, each jumper structure comprising:
• a first metal landing pad located in the second metal layer and electrically connected to the write bit line and to the global write bit line;
• a second metal landing pad located in the second metal layer and electrically connected to the inverse write bit line and the inverse global write bit line;
• and
• a third metal landing pad located in the second metal layer and electrically connected to the read bit line and a peripheral metal line of the peripheral logic circuit, the peripheral metal line located in the first metal layer.