# US 2016/0366759 A1 · Printed circuit board with reduced cross-talk > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0366759 A1 - Document ID: US20160366759A1 - Status: Published application - Kind: A1 - Application number: 14/461,900 - Filed: 2014-08-18 - Published: 2016-12-15 - Earliest claimed: 2012-01-06 - Assignees: Cray Inc. - Applicants: Cray Inc. - Inventors: Hyunjun Kim; Jeffrey Scott Conger; Gregory Erwin Scott - Web page: https://patentgrep.com/patent/US20160366759A1 ## CPC - H05K 1/0225: {Single or multiple openings in a shielding, ground or power plane (H05K1/0227 takes precedence)} - H05K 1/0219: {Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors} - H05K 1/0222: {for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence} - H05K 1/0245: {Lay-out of balanced signal pairs, e.g. differential lines or twisted lines} - H05K 1/0298: {Multilayer circuits} - H05K 1/114: {Pad being close to via, but not surrounding the via} - H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)} - H05K 3/4007: {Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465)} - H05K 3/42: Plated through-holes {or plated via connections} - H05K 2201/093: Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein - H05K 2201/09336: Signal conductors in same plane as power plane - H05K 2201/09609: Via grid, i.e. two-dimensional array of vias or holes in a single plane - H05K 2201/09618: Via fence, i.e. one-dimensional array of vias - Y10T 29/49155: Manufacturing circuit on or in base - Y10T 29/49165: by forming conductive walled aperture in base - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract A multi-layer printed circuit board has a number of landing pads that are configured to engage a connector secured thereto. Between the landing pads associated with different signals is at least one micro via that is electrically connected to a ground plane on an outer surface of the multi-layer printed circuit board, and a ground plane on an inner layer of the multi-layer printed circuit board. ## Claims ### Claim 1 A multi-layer printed circuit board, comprising: a multi-layer board having a number of conductive traces for carrying signals and one or more ground planes that are connected by a number of conductive grounding vias; wherein the printed circuit board includes a series of conductive landing pads on an outer layer of the printed board that are configured to electrically engage contacts of a connector mounted on the printed circuit board and further includes one or more micro vias positioned between landing pads associated with different signals, wherein each micro via is electrically connected to a ground plane on the outer layer of the printed circuit board and a ground plane on an inner layer of the printed circuit board. ### Claim 2 (depends on 1) The multi-layer printed circuit board of claim 1, wherein signals are carried differentially on a pair of traces, such that there are two landing pads for each signal that is electrically coupled to the connector, and wherein each micro via is positioned between the two landing pads associated with different signals. ### Claim 3 (depends on 1) The multi-layer printed circuit board of claim 1, wherein the landing pads are aligned and the micro vias are symmetrically placed between the landing pads associated with different signals. ### Claim 4 (depends on 1) The multi-layer printed circuit board of claim 1, wherein the landing pads are aligned and the micro vias are asymmetrically placed between the landing pads associated with different signals. ### Claim 5 (depends on 1) The multi-layer printed circuit board of claim 1, wherein the micro vias extend between an outer layer of the printed circuit board and an adjacent layer of the printed circuit board. ### Claim 6 (depends on 1) The multi-layer printed circuit board of claim 1, wherein the micro vias extend between an outer layer of the printed circuit board and a non-adjacent layer of the printed circuit board. ### Claim 7 A method of manufacturing a multi-layer printed circuit board comprising: forming a number of landing pads on an outer layer of the printed circuit board that electrically connect to a connector; forming a portion of a ground plane between landing pads that are associated with different signals to be coupled to the connector; and forming one or more micro vias between the landing pads that are associated with different signals, wherein the micro vias are electrically connected to a ground plane on the outer layer of the circuit board and to a ground plane on an inner layer of the circuit board. ### Claim 8 A multi-layer printed circuit board, comprising: a plurality of circuit board layers including an outer layer with landing pads there that connect to a circuit board connector; one or more circuit tracers on which signals are routed to different landing pads; and one or more shielding structures positioned between the landing pads associated with different signals. ### Claim 9 (depends on 8) The multi-layer printed circuit board of claim 8, wherein the shielding structures are micro vias. ### Claim 10 (depends on 9) The multi-layer printed circuit board of claim 9, wherein the micro vias have one end electrically connected to a grounding pad adjacent to the landing pads and another end electrically connected to a grounding pad on an inner layer of the multi-layer printed circuit board.