# US 2016/0366358 A1 · Counting circuit, image sensing device with the counting circuit and read-out method of the image sensing device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0366358 A1 - Document ID: US20160366358A1 - Status: Published application - Kind: A1 - Application number: 14/924,418 - Filed: 2015-10-27 - Published: 2016-12-15 - Earliest claimed: 2015-06-09 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Min-Seok SHIN; Jung-Eun SONG - Web page: https://patentgrep.com/patent/US20160366358A1 ## CPC - H03K 21/026: {comprising logic circuits} - H04N 25/616: involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling - H04N 25/618: for random or high-frequency noise - H04N 25/7795: {Circuitry for generating timing or clock signals} - H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A read-out method of an image sensing device includes: firstly counting a reset signal of a pixel signal based on a first analog gain during a first period of a unit row period; storing a result of the first counting as a previous counting result; secondly counting the reset signal based on a second analog gain; thirdly counting a data signal of the pixel signal based on the second analog gain during a second period following the first period in the unit row period; storing a first counting signal corresponding to results of the second counting and the third counting; fourthly counting the data signal based on the first analog gain during a third period following the second period in the unit row period; and storing a second counting signal corresponding to the previous counting result and a result of the fourth counting. ## Claims ### Claim 1 A counting circuit comprising: a sampling unit suitable for sampling an inverted bit signal, which corresponds to any one of inverted signals of a bit signal and a previous bit signal, as the bit signal in response to a counting target clock signal; a first latch unit suitable for latching the bit signal, as which the sampling unit samples the inverted bit signal corresponding to the inverted signal of the bit signal during a first period, as the previous bit signal at a first time point in response to a first latch control signal, and suitable for providing the previous bit signal to the sampling unit at a third time point in response to a load control signal; a second latch unit suitable for latching the bit signal, as which the sampling unit samples the inverted bit signal corresponding to the inverted signal of the bit signal during a second period, as a first counting bit signal at a second time point in response to a second latch control signal; and a third latch unit suitable for latching the bit signal, as which the sampling unit samples the inverted bit signal corresponding to the inverted signal of the previous bit signal during a third period, as a second counting bit signal at a fourth time point in response to a third latch control signal. ### Claim 2 (depends on 1) The counting circuit of claim 1, further comprising: a selection unit suitable for selecting any one of the bit signal and the previous bit signal as a selected bit signal in response to the load control signal; and an inversion unit suitable for generating the inverted bit signal by inverting the selected bit signal. ### Claim 3 (depends on 1) The counting circuit of claim 1, further comprising an offset cancellation unit suitable for performing a digital double sampling (DDS) operation on the bit signal. ### Claim 4 (depends on 3) The counting circuit of claim 3, wherein the DDS operation comprises any one of single-direction counting, up/down counting, and Bit-Wise Inversion (BWI). ### Claim 5 (depends on 3) The counting circuit of claim 3, wherein the sampling unit samples the inverted bit signal as the bit signal in response to the counting target clock signal, into which a second reset signal and a second data signal are sequentially reflected during the second period, wherein the offset cancellation unit performs the DDS operation on the bit signal during the second period, and wherein the second latch unit latches the bit signal, on which the DDS operation is performed, as the first counting bit signal. ### Claim 6 (depends on 5) The counting circuit of claim 5, wherein the sampling unit samples the inverted bit signal as the bit signal in response to the counting target clock signal, into which a first reset signal is reflected during the first period, wherein the sampling unit samples the inverted bit signal as the bit signal, on which the DDS operation has been performed regardless of the offset cancellation unit, in response to the counting target clock signal, into which a first data signal is reflected during the third period, and wherein the third latch unit latches the bit signal, on which the DDS operation is performed, as the second counting bit signal. ### Claim 7 An image sensing device comprising: a pixel block suitable for generating a pixel signal corresponding to a reset signal during a reset period of a unit row period, and generating the pixel signal corresponding to a data signal during a data period of the unit row period; a ramp signal generation block suitable for generating a ramp signal which ramps a plurality of times with different slopes during the reset period and ramps a plurality of times with different slopes during the data period; a comparison block suitable for generating a comparison signal which includes a first comparison result obtained by comparing the ramp signal and the reset signal a plurality of times during the reset signal, and a second comparison result obtained by comparing the ramp signal and the data signal a plurality of times during the data period; and a counting block suitable for generating a plurality of counting signals corresponding to the first and second comparison results in response to a counting clock signal, a plurality of latch control signals, one or more load control signals, and the comparison signal during the unit row period. ### Claim 8 (depends on 7) The image sensing device of claim 7, wherein the counting block generates the plurality of counting signals through correlated double sampling (CDS). ### Claim 9 (depends on 7) The image sensing device of claim 7, wherein the counting block comprises: a counting control unit suitable for generating a counting target clock signal in response to the counting clock signal and the comparison signal; a sampling unit suitable for sampling an inverted bit signal, which corresponds to any one of inverted signals of a bit signal and a previous bit signal, as the bit signal in response to the counting target clock signal; a first latch unit suitable for latching the bit signal, as which the sampling unit samples the inverted bit signal corresponding to the inverted signal of the bit signal during a first period, as the previous bit signal at a first time point in response to a first latch control signal of the plurality of latch control signals, and suitable for providing the previous bit signal to the sampling unit at a third time point in response to the load control signal; a second latch unit suitable for latching the bit signal, as which the sampling unit samples the inverted bit signal corresponding to the inverted signal of the bit signal during a second period, as a first counting bit signal at a second time point in response to a second latch control signal of the plurality of latch control signals; and a third latch unit suitable for latching the bit signal, as which the sampling unit samples the inverted bit signal corresponding to the inverted signal of the previous bit signal during a third period, as a second counting bit signal at a fourth time point in response to a third latch control signal of the plurality of latch control signals. ### Claim 10 (depends on 9) The image sensing device of claim 9, wherein the counting block further comprises: a selection unit suitable for selecting any one of the bit signal and the previous bit signal as a selected bit signal in response to the load control signal; and an inversion unit suitable for generating the inverted bit signal by inverting the selected bit signal. ### Claim 11 (depends on 9) The image sensing device of claim 9, wherein the counting block further comprises an offset cancellation unit suitable for performing a digital double sampling (DDS) operation on the bit signal. ### Claim 12 (depends on 11) The image sensing device of claim 11, wherein the DDS operation comprises any one of single-direction counting, up/down counting, and Bit-Wise Inversion (BWI). ### Claim 13 (depends on 11) The image sensing device of claim 11, wherein the sampling unit samples the inverted bit signal as the bit signal in response to the counting target clock signal, into which a second reset signal and a second data signal are sequentially reflected during the second period, wherein the offset cancellation unit performs the DDS operation on the bit signal during the second period, and wherein the second latch unit latches the bit signal on which the DDS operation is performed, as the first counting bit signal. ### Claim 14 (depends on 13) The image sensing device of claim 13, wherein the sampling unit samples the inverted bit signal as the bit signal in response to the counting target clock signal, into which a first reset signal is reflected during the first period, wherein the sampling unit samples the inverted bit signal as the bit signal, on which the DDS operation has been performed regardless of the offset cancellation unit, in response to the counting target clock signal, into which a first data signal is reflected during the third period, and wherein the third latch unit latches the bit signal on which the DDS operation is performed, as the second counting bit signal. ### Claim 15 (depends on 9) The image sensing device of claim 9, wherein the first period comprises the front part of the reset period, wherein the second period comprises the rear part of the reset period and the front part of the data period, and wherein the third period comprises the rear part of the data period. ### Claim 16 A read-out method of an image sensing device, the read-out method comprising: performing a first counting a reset signal of a pixel signal based on a first analog gain during a first period of a unit row period; storing a result of the first counting as a previous counting result; performing a second counting the reset signal based on a second analog gain; performing a third counting a data signal of the pixel signal based on the second analog gain during a second period following the first period in the unit row period; storing a first counting signal corresponding to results of the second counting and the third counting; performing a fourth counting the data signal based on the first analog gain during a third period following the second period in the unit row period; and storing a second counting signal corresponding to the previous counting result and a result of the fourth counting. ### Claim 17 (depends on 16) The read-out method of claim 16, wherein the third counting generates the first counting signal through a digital double sampling (DDS) operation. ### Claim 18 (depends on 17) The read-out method of claim 17, wherein the fourth counting generates the second counting signal through the DDS operation. ### Claim 19 (depends on 18) The read-out method of claim 18, wherein the DDS operation comprises Bit-Wise Inversion (BWI). ### Claim 20 (depends on 16) The read-out method of claim 16, wherein the first period comprises the front part of the reset period included in the first unit row period, wherein the second period comprises the rear part of the reset period and the front part of the data period included in the unit row period, and wherein the third period comprises the rear part of the data period.