# US 2016/0366307 A1 · Image data receiving device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2016/0366307 A1 - Document ID: US20160366307A1 - Status: Published application - Kind: A1 - Application number: 14/980,059 - Filed: 2015-12-28 - Published: 2016-12-15 - Earliest claimed: 2015-06-10 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Takashi Kanoh - Web page: https://patentgrep.com/patent/US20160366307A1 ## CPC - H04N 5/04: Synchronising (for television systems using pulse code modulation H04N7/56) - G09G 5/00: Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators (image data processing or generation, in general G06T) - G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)} - H04N 5/44: Receiver circuitry {for the reception of television signals according to analogue transmission standards} (H04N5/14 takes precedence) - G09G 2330/08: Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared - G09G 2330/12: Test circuits or failure detection circuits included in a display system, as permanent part thereof - G09G 2352/00: Parallel handling of streams of display data - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract According to one embodiment, there is provided an image data receiving device including 1st to Kth lane reproduction circuits, 1st to Kth timing adjustment circuits, 1st to Kth lane reproduction outputs, and 1st to (K−1)th selectors. The Nth lane reproduction circuit transmits data of an nth pixel. The (N+1)th lane reproduction circuit transmits data of an (n+1)th pixel adjacent to the nth pixel. The Nth timing adjustment circuit has an input terminal electrically connected to the Nth lane reproduction circuit. The (N+1)th timing adjustment circuit has an input terminal electrically connected to the (N+1)th lane reproduction circuit. The Nth lane reproduction output can be electrically connected to an output terminal of the Nth timing adjustment circuit. The Nth selector can electrically connect one of the output terminal of the Nth timing adjustment circuit and the output terminal of the (N+1)th timing adjustment circuit to the (N+1)th lane reproduction output. ## Claims ### Claim 1 An image data receiving device comprising: 1st to Kth lane reproduction circuits, where K is an integer of two or greater; 1st to Kth timing adjustment circuits; 1st to Kth lane reproduction outputs; and 1st to (K−1)th selectors, if letting N be a positive integer smaller than K and n be a positive integer, the Nth lane reproduction circuit transmitting data of an nth pixel, the (N+1)th lane reproduction circuit transmitting data of an (n+1)th pixel adjacent to the nth pixel, the Nth timing adjustment circuit having an input terminal electrically connected to the Nth lane reproduction circuit, the (N+1)th timing adjustment circuit having an input terminal electrically connected to the (N+1)th lane reproduction circuit, the Nth lane reproduction output being able to be electrically connected to an output terminal of the Nth timing adjustment circuit, and the Nth selector being able to electrically connect one of the output terminal of the Nth timing adjustment circuit and the output terminal of the (N+1)th timing adjustment circuit to the (N+1)th lane reproduction output. ### Claim 2 (depends on 1) The image data receiving device according to claim 1, wherein the Nth selector electrically connects one of an output terminal of the (N−1)th selector and the output terminal of the (N+1)th timing adjustment circuit to the (N+1)th lane reproduction output. ### Claim 3 (depends on 1) The image data receiving device according to claim 1, wherein letting m be a positive integer smaller than or equal to n, the 1st lane reproduction circuit transmits data of an mth pixel, wherein the second lane reproduction circuit transmits data of an (m+1)th pixel, wherein the Kth lane reproduction circuit transmits data of an (m−1)th pixel, wherein the Kth timing adjustment circuit has an input terminal electrically connected to the Kth lane reproduction circuit, wherein the (K−1)th selector electrically connects one of an output terminal of the (K−2)th selector and the output terminal of the Kth timing adjustment circuit to the Kth lane reproduction output, and wherein the image data receiving device further comprises: a delay circuit that has an input terminal electrically connected to the output terminal of the (K−1)th selector, and a Kth selector that electrically connects one of an output terminal of the delay circuit and the output terminal of the 1st timing adjustment circuit to the 1st lane reproduction output. ### Claim 4 (depends on 3) The image data receiving device according to claim 3, wherein the 1st lane reproduction circuit transmits data of the mth pixel during a first period, wherein the 2nd lane reproduction circuit transmits data of the (m+1)th pixel during the first period, and wherein the Kth lane reproduction circuit transmits data of the (m−1)th pixel during a second period preceding the first period. ### Claim 5 (depends on 1) The image data receiving device according to claim 1, further comprising 1st to (K−1)th error detection circuits, wherein the Nth error detection circuit has an input terminal electrically connected to the (N+1)th lane reproduction circuit and an output terminal that can be electrically connected to a control terminal of the Nth selector. ### Claim 6 (depends on 3) The image data receiving device according to claim 3, further comprising 1st to Kth error detection circuits, wherein the Nth error detection circuit has an input terminal electrically connected to the (N+1)th lane reproduction circuit and an output terminal that can be electrically connected to a control terminal of the Nth selector, and wherein the Kth error detection circuit has an input terminal electrically connected to the 1st lane reproduction circuit and an output terminal that can be electrically connected to a control terminal of the Kth selector. ### Claim 7 (depends on 5) The image data receiving device according to claim 5, wherein if the 1st error detection circuit has detected a data error in the 2nd lane reproduction circuit, the 1st selector electrically connects the output terminal of the 1st timing adjustment circuit to the 2nd lane reproduction output and, if the 1st error detection circuit has not detected a data error in the 2nd lane reproduction circuit, electrically connects the output terminal of the 2nd timing adjustment circuit to the 2nd lane reproduction output, and wherein letting N be an integer of two or greater that is smaller than K, if the Nth error detection circuit has detected a data error in the (N+1)th lane reproduction circuit, the Nth selector electrically connects the output terminal of the (N−1)th selector to the (N+1)th lane reproduction output and, if the Nth error detection circuit has not detected a data error in the (N+1)th lane reproduction circuit, electrically connects the output terminal of the (N+1)th timing adjustment circuit to the (N+1)th lane reproduction output. ### Claim 8 (depends on 6) The image data receiving device according to claim 6, wherein if the 1st error detection circuit has detected a data error in the second lane reproduction circuit, the 1st selector electrically connects the output terminal of the 1st timing adjustment circuit to the second lane reproduction output and, if the 1st error detection circuit has not detected a data error in the second lane reproduction circuit, electrically connects the output terminal of the second timing adjustment circuit to the 2nd lane reproduction output, wherein letting N be an integer of two or greater that is smaller than K, if the Nth error detection circuit has detected a data error in the (N+1)th lane reproduction circuit, the Nth selector electrically connects the output terminal of the (N−1)th selector to the (N+1)th lane reproduction output and, if the Nth error detection circuit has not detected a data error in the (N+1)th lane reproduction circuit, electrically connects the output terminal of the (N+1)th timing adjustment circuit to the (N+1)th lane reproduction output, and wherein if the Kth error detection circuit has detected a data error in the 1st lane reproduction circuit, the Kth selector electrically connects the output terminal of the delay circuit to the 1st lane reproduction output and, if the Kth error detection circuit has not detected a data error in the 1st lane reproduction circuit, electrically connects the output terminal of the 1st timing adjustment circuit to the 1st lane reproduction output. ### Claim 9 (depends on 1) The image data receiving device according to claim 1, further comprising a reference selection circuit that supplies a reference clock as a clock of reading operation to the 1st to Kth timing adjustment circuits, wherein the Nth timing adjustment circuit has a FIFO memory into which pixel data is written synchronously with a clock received from the Nth lane reproduction circuit and which outputs the pixel data synchronously with the clock of reading operation received from the reference selection circuit. ### Claim 10 (depends on 9) The image data receiving device according to claim 9, wherein the reference selection circuit selects a lane reproduction circuit of a reference from among the 1st to Kth lane reproduction circuits and supplies a clock received from the lane reproduction circuit of the reference as the clock of reading operation, to the 1st to Kth timing adjustment circuits. ### Claim 11 (depends on 6) The image data receiving device according to claim 6, further comprising 1st to Kth replacement control circuits, wherein the Nth replacement control circuit has a control terminal to which a replacement control signal is supplied, an input terminal electrically connected to the Nth error detection circuit, an input terminal fixed at a de-assert level, an input terminal fixed at an assert level, and an output terminal electrically connected to the control terminal of the Nth selector. ### Claim 12 (depends on 11) The image data receiving device according to claim 11, wherein the Nth replacement control circuit switches between an operation of allowing an error detection flag received from the Nth error detection circuit to pass through to be output to the control terminal of the Nth selector, an operation of outputting the de-assert level to the control terminal of the selector, and an operation of outputting the assert level to the control terminal of the selector. ### Claim 13 An image data receiving device comprising: 1st to Kth lane reproduction circuits, where K is an integer of two or greater; 1st to Kth timing adjustment circuits; 1st to Kth lane reproduction outputs; and 1st to Kth selectors, if letting N be a positive integer smaller than K and n be a positive integer, the Nth lane reproduction circuit transmitting data of an nth pixel, the (N+1)th lane reproduction circuit transmitting data of an (n+1)th pixel adjacent to the nth pixel, the Nth timing adjustment circuit having an input terminal electrically connected to the Nth lane reproduction circuit, the (N+1)th timing adjustment circuit having an input terminal electrically connected to the (N+1)th lane reproduction circuit, the Nth lane reproduction output being able to be electrically connected to an output terminal of the Nth timing adjustment circuit, and the Nth selector being able to electrically connect one of the output terminal of the Nth timing adjustment circuit and the output terminal of the (N+1)th timing adjustment circuit to the Nth lane reproduction output. ### Claim 14 (depends on 13) The image data receiving device according to claim 13, wherein the Nth selector electrically connects one of the output terminal of the Nth timing adjustment circuit and an output terminal of the (N+1)th selector to the Nth lane reproduction output. ### Claim 15 (depends on 13) The image data receiving device according to claim 13, further comprising 1st to Kth delay circuits, wherein the Nth delay circuit is connected between the output terminal of the Nth timing adjustment circuit and an input terminal of the Nth selector, and wherein the Kth selector electrically connects one of the output terminal of the 1st timing adjustment circuit and an output terminal of the Kth delay circuit to the Kth lane reproduction output. ### Claim 16 (depends on 15) The image data receiving device according to claim 15, wherein the 1st lane reproduction circuit transmits data of the mth pixel during a first period, wherein the second lane reproduction circuit transmits data of the (m+1)th pixel during the first period, and wherein the Kth lane reproduction circuit transmits data of the (m−1)th pixel during a second period preceding the first period. ### Claim 17 (depends on 13) The image data receiving device according to claim 13, further comprising 1st to Kth error detection circuits, wherein the Nth error detection circuit has an input terminal electrically connected to the Nth lane reproduction circuit and an output terminal that can be electrically connected to a control terminal of the Nth selector. ### Claim 18 (depends on 17) The image data receiving device according to claim 17, wherein if the Nth error detection circuit has detected a data error in the Nth lane reproduction circuit, the Nth selector electrically connects the output terminal of the (N+1)th selector to the Nth lane reproduction output and, if the Nth error detection circuit has not detected a data error in the Nth lane reproduction circuit, electrically connects the output terminal of the Nth timing adjustment circuit to the Nth lane reproduction output. ### Claim 19 (depends on 13) The image data receiving device according to claim 13, further comprising a reference selection circuit that selects a lane reproduction circuit of a reference from among the 1st to Kth lane reproduction circuits and that supplies a clock received from the lane reproduction circuit of the reference as a clock of reading operation, to the 1st to Kth timing adjustment circuits, wherein the Nth timing adjustment circuit has a FIFO memory into which pixel data is written synchronously with a clock received from the Nth lane reproduction circuit and which outputs the pixel data synchronously with the clock of reading operation received from the reference selection circuit. ### Claim 20 (depends on 19) The image data receiving device according to claim 19, further comprising 1st to Kth replacement control circuits, wherein the Nth replacement control circuit has a control terminal to which a replacement control signal is supplied, an input terminal electrically connected to the Nth error detection circuit, an input terminal fixed at a de-assert level, an input terminal fixed at an assert level, and an output terminal electrically connected to the control terminal of the Nth selector.