# US 2016/0366114 A1 · Inter-bus communication interface device

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- Number: US 2016/0366114 A1
- Document ID: US20160366114A1
- Status: Published application
- Kind: A1
- Application number: 15/181,201
- Filed: 2016-06-13
- Published: 2016-12-15
- Earliest claimed: 2003-03-28
- Assignees: Cypress Semiconductor Corporation
- Applicants: Cypress Semiconductor Corporation
- Inventors: Kenichi Iizuka; Kumiko Toshimori; Machiko MIKAMI
- Web page: https://patentgrep.com/patent/US20160366114A1

## CPC

- H04L 63/0471: {applying encryption by an intermediary, e.g. receiving clear information at the intermediary and encrypting the received information at the intermediary before forwarding}
- G06F 13/24: using interrupt (G06F13/32 takes precedence)
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices}
- G06F 13/4063: {Device-to-bus coupling}
- G06F 21/602: {Providing cryptographic facilities or services}
- G06F 21/72: in cryptographic circuits
- H04L 9/0643: {Hash functions, e.g. MD5, SHA, HMAC or f9 MAC}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Described herein is a security network controller having a main bus to which is coupled a central processing unit, a cryptographic processing circuit, a security control circuit, and a memory controller. The security control circuit is configured to receive data stored in memory from the memory controller over the main bus and send the data over a first dedicated bus to the cryptographic processing circuit to obtain encrypted data. The security control circuit is further configured to receive the encrypted data over the first dedicated bus from the cryptographic processing circuit and send the encrypted data to the memory controller over the main bus. The memory controller stores the encrypted data in memory of the security network controller.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A security network controller comprising:
a main bus;
a central processing unit (CPU) coupled to the main bus;
a cryptographic processing circuit coupled to the main bus;
a security control circuit coupled to the main bus;
a first dedicated bus coupled between the cryptographic processing circuit and the security control circuit;
a memory controller coupled to the main bus and memory, wherein the security control circuit is configured to:
receive data stored in memory from the memory controller;
send the data over the first dedicated bus to the cryptographic processing circuit to obtain encrypted data;
receive the encrypted data over the first dedicated bus from the cryptographic processing circuit; and
send the encrypted data to the memory controller, the memory controller to store the encrypted data in the memory.

### Claim 22 (depends on 21)

The security network controller of claim 21, further comprising:
a hash function processing circuit coupled to the main bus; and
a second dedicated bus coupled between the hash function processing circuit and the security control circuit, wherein the security control circuit is further configured to:
receive the encrypted data stored in memory from the memory controller;
send the encrypted data over the second dedicated bus to the hash function processing circuit to generate a hash value;
receive the hash value over the second dedicated bus from the hash function processing circuit; and
send the hash value to the CPU to be stored with the encrypted data stored in the memory.

### Claim 23 (depends on 22)

The security network controller of claim 22, further comprising a communication interface, and wherein the CPU is configured to:
generate a packet for transmission from the encrypted data and the hash value stored in the memory; and
distribute the packet via the communication interface to a terminal unit over the Internet.

### Claim 24 (depends on 21)

The security network controller of claim 21, wherein the security control circuit is configured to:
receive the data stored in memory from the memory controller by a first DMA transfer over the main bus; and
send the encrypted data to the memory controller by a second DMA transfer over the main bus,

### Claim 25 (depends on 21)

The security network controller of claim 21, wherein the security control circuit is further configured to receive additional data stored in the memory over the main bus while sending the data over the first dedicated bus to the cryptographic processing circuit to obtain encrypted data.

### Claim 26 (depends on 22)

The security network controller of claim 22, wherein the security control circuit is further configured to receive additional data stored in the memory over the main bus while sending the encrypted data over the second dedicated bus to the hash function processing circuit to generate the hash value.

### Claim 27 (depends on 21)

The security network controller of claim 21, further comprising an external connection interface coupled to the main bus and coupled to a main CPU that is external to the security network controller, wherein the memory controller is configured to receive the data from the main CPU over the external connection interface and over the main bus.

### Claim 28 (depends on 21)

The security network controller of claim 21, further comprising:
a hash function processing circuit coupled to the main bus;
a second dedicated bus coupled between the hash function processing circuit and the security control circuit; and
a communication interface with an input buffer, wherein the communication interface is configured to receive a frame at the input buffer, wherein the CPU is configured to perform header processing of a packet contained in the frame, wherein the security control circuit is further configured to:
receive the packet from the CPU over the main bus;
send encrypted data from the packet over the second dedicated bus to the hash function processing circuit to generate a hash value;
receive the hash value from the hash function processing circuit over the second dedicated bus;
compare the hash value with a second hash value in the packet to authenticate the frame;
when the frame is authenticated, send the encrypted data from the packet over the first dedicated bus to the cryptographic processing circuit to obtain decrypted data;
receive the decrypted data from the cryptographic processing circuit over the first dedicated bus; and
send the decrypted data over the main bus to be stored in the memory.

### Claim 29 (depends on 28)

The security network controller of claim 28, further comprising an external connection interface coupled to the main bus and coupled to a main CPU that is external to the security network controller, wherein the memory controller is configured to send the decrypted data to the main CPU over the main bus and the external connection interface.

### Claim 30

A method of operating a security network controller, the method comprising:
receiving, at a security control circuit, data stored in memory from a memory controller;
sending, by the security control circuit, the data over a first dedicated bus to a cryptographic processing circuit to obtain encrypted data;
encrypting, by the cryptographic processing circuit, the data to obtain encrypted data;
receiving, by the security control circuit, the encrypted data over the first dedicated bus from the cryptographic processing circuit;
transferring, by the security control circuit, the encrypted data to the memory controller; and
storing, by the memory controller, the encrypted data in the memory.

### Claim 31 (depends on 30)

The method of claim 30, wherein the receiving the data stored in memory comprises receiving, at the security control circuit, the data stored in the memory by a direct memory access (DMA) transfer by the memory controller over the main bus, and wherein the transferring the encrypted data to the memory controller comprises transferring, by the security control circuit, the encrypted data to the memory controller by a second DMA transfer over the main bus.

### Claim 32 (depends on 30)

The method of claim 30, further comprising:
receiving, by the security control circuit, the encrypted data stored in memory by the memory controller;
sending, by the security control circuit, the encrypted data over a second dedicated bus to a hash function processing circuit;
generating, by the hash function processing circuit, a hash value from the encrypted data;
receiving, by the security control circuit, the hash value over the second dedicated bus from the hash function processing circuit;
sending, by the security control circuit, the hash value to a central processing unit (CPU) of the security network controller over the main bus; and
storing, by the CPU, the hash value with the encrypted data stored in the memory.

### Claim 33 (depends on 30)

The method of claim 30, further comprising:
generating, by a central processing unit (CPU) of the security network controller, a packet for transmission from the encrypted data and the hash value stored in the memory; and
distributing, by the CPU, the packet via a communication interface to a terminal unit over the Internet.

### Claim 34 (depends on 30)

The method of claim 30, further comprising receiving, by the security control circuit, additional data stored in the memory over the main bus while sending the data over the first dedicated bus to the cryptographic processing circuit.

### Claim 35 (depends on 31)

The method of claim 31, further comprising receiving, by the security control circuit, additional data stored in the memory over the main bus while sending the encrypted data over the second dedicated bus to the hash function processing circuit.

### Claim 36 (depends on 30)

The method of claim 30, further comprising receiving, at an external connection interface, the data from a main CPU that is external to the security network.

### Claim 37 (depends on 30)

The method of claim 30, further comprising:
receiving a frame at an input buffer of a communication interface of the security network controller;
performing, by a central processing unit (CPU) of the security network controller, header processing of a packet contained in the frame;
receiving, by the security control circuit, the packet over the main bus;
sending, by the security control circuit, encrypted data from the packet over a second dedicated bus to a hash function processing circuit;
generating, by the hash function processing circuit, a hash value from the encrypted data;
receiving, by the security control circuit, the hash value from the hash function processing circuit over the second dedicated bus; and
comparing, by the security control circuit, the hash value with a second hash value in the packet to authenticate the frame.

### Claim 38 (depends on 37)

The method of claim 37, further comprising:
when the data is authenticated, sending the encrypted data from the packet over the first dedicated bus to the cryptographic processing circuit by the security control circuit;
decrypting, by the cryptographic processing circuit, the encrypted data to obtain decrypted data;
receiving, by the security control circuit, the decrypted data from the cryptographic processing circuit over the first dedicated bus; and
sending, by the security control circuit, the decrypted data over the main bus to be stored in the memory; and
sending, by the memory controller, the decrypted data to a main CPU over the main bus and an external connection interface coupled between the main bus and the main CPU, wherein the main CPU is external to the security network controller.

### Claim 39

A system comprising:
a main central processing unit (CPU);
a security network controller comprising an external connection interface coupled to the main CPU and a communication interface coupled to a network, wherein the security network controller further comprises:
a main bus;
a CPU coupled to the main bus;
a cryptographic processing circuit coupled to the main bus;
a security control circuit coupled to the main bus;
a first dedicated bus coupled between the cryptographic processing circuit and the security control circuit;
a memory controller coupled to the main bus and memory, wherein the security control circuit is configured to:
receive data stored in memory from the memory controller;
send the data over the first dedicated bus to the cryptographic processing circuit to obtain encrypted data;
receive the encrypted data over the first dedicated bus from the cryptographic processing circuit; and
send the encrypted data to the memory controller, the memory controller to store the encrypted data in the memory.

### Claim 40 (depends on 39)

The system of claim 39, wherein the security network controller further comprises:
a hash function processing circuit coupled to the main bus; and
a second dedicated bus coupled between the hash function processing circuit and the security control circuit, wherein the security control circuit is further configured to:
receive the encrypted data stored in memory from the memory controller;
send the encrypted data over the second dedicated bus to the hash function processing circuit to generate a hash value;
receive the hash value over the second dedicated bus from the hash function processing circuit;
send the hash value to the CPU to be stored with the encrypted data stored in the memory, wherein the CPU is configured to:
generate a packet for transmission from the encrypted data and the hash value stored in the memory; and
distribute the packet via the communication interface to a terminal unit over the network.