# US 2016/0365366 A1 · Metallic oxide thin film transistor, array substrate and their manufacturing methods, display device

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- Number: US 2016/0365366 A1
- Document ID: US20160365366A1
- Status: Published application
- Kind: A1
- Application number: 14/771,267
- Filed: 2014-12-12
- Published: 2016-12-15
- Earliest claimed: 2014-08-06
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.
- Inventors: Lei ZHAO; Wei GUO
- Web page: https://patentgrep.com/patent/US20160365366A1

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/80: characterised by the materials
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 10/00: Bonding of wafers, substrates or parts of devices
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 50/282: {of inorganic materials}
- H10P 50/69: {using masks for semiconductor materials}
- H10P 76/204: {of organic photoresist masks}
- H10P 14/6329: {using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition}
- H10P 14/69394: {the material containing titanium, e.g. TiO2}
- H10P 50/285: {of materials not containing Si, e.g. PZT or Al2O3}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a metallic oxide thin film transistor and its manufacturing method, an array substrate and its manufacturing method, as well as a display device, which is belong to the field of thin film transistor manufacturing technology. The method for manufacturing the metallic oxide thin film transistor comprises a step of forming patterns of an oxide active layer and an etch stopping layer through a one-time patterning process.

## Claims

### Claim 1

A method for manufacturing a metallic oxide thin film transistor, comprising a step of forming patterns of an oxide active layer and an etch stopping layer through a one-time patterning process.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the etch stopping layer is made of TiO2 or a mixture of TiO2 and CeO2.

### Claim 3 (depends on 1, 2)

The method according to claim 1 or 2, wherein in the one-time patterning process, the pattern of an etch stopping layer is formed by a dry etching process, and the pattern of an oxide active layer is formed by a wet etching process.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the step of forming patterns of an oxide active layer and an etch stopping layer of the thin film transistor by a one-time patterning process comprises:
depositing an metallic oxide semiconductor layer and an etch stopping layer on a substrate successively;
coating a photoresist onto the etch stopping layer, exposing and developing with a halftone or a greytone mask plate, so as to form patterns including a photoresist unreserved region, a photoresist partly reserved region and a photoresist completely reserved region;
etching off the etch stopping layer in the photoresist unreserved region through a dry etching process, and etching off the metallic oxide semiconductor layer in the photoresist unreserved region through a wet etching process, so as to form a pattern of an metallic oxide semiconductor layer;
removing the photoresist in the photoresist partly reserved region through ashing, etching off the etch stopping layer in the photoresist partly reserved region through a wet etching process, so as to form a pattern of the etch stopping layer;
subjecting the metallic oxide semiconductor layer which is not covered by the etch stopping layer to plasma treatment, so as to form the oxide active layer; and
peeling off the photoresist in the photoresist completely reserved region.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the step of depositing the etch stopping layer on the substrate comprises:
subjecting Ti(OC4H9)4 to bubbling treatment with N2; and
depositing Ti(OC4H9)4 after being subjected to the bubbling treatment on the substrate by means of metal vapor deposition under an oxygen atmosphere, so as to form a TiO2 film; or depositing metal Ti on the substrate by means of direct current magnetron sputtering under an oxygen atmosphere, so as to form the TiO2 film; or depositing a mixture of CeO2 and TiO2 on a substrate by means of magnetron sputtering, so as to form a film of a mixture of CeO2 and TiO2.

### Claim 6 (depends on 4, 5)

The method according to claim 4 or 5, wherein the substrate comprises a base substrate and a portion of film layer formed on the base substrate.

### Claim 7 (depends on 4)

The method according to claim 4, wherein an etchant gas used in the dry etching process is CF4, a mixture of CF4 and O2, CCl4, BCl3, or a mixture of BCl3 and Cl2.

### Claim 8 (depends on 5)

The method according to claim 5, wherein based on a total weight of the mixture of CeO2 and TiO2, TiO2 is of a content of about 40 wt % to about 50 wt %.

### Claim 9 (depends on 4)

The method according to claim 4, comprising:
providing a base substrate;
forming a gate electrode and a gate line on the base substrate through a one-time patterning process;
forming a gate insulting layer on the substrate formed with the gate electrode and the gate line;
forming patterns of the oxide active layer and the etch stopping layer on the gate insulating layer through a one-time patterning process; and
forming a source electrode, a drain electrode and a data line on the substrate formed with the patterns of the oxide active layer and the etch stopping layer through a one-time patterning process.

### Claim 10 (depends on 1)

A method for manufacturing a metallic oxide thin film transistor array substrate, comprising: after manufacturing the metallic oxide thin film transistor according to claim 1, forming a passivation layer with a via hole on the substrate formed with a source electrode, a drain electrode and a data line through a one-time patterning process; and forming a pixel electrode on the passivation layer through a one-time patterning process, wherein the pixel electrode is connected to the drain electrode through the via hole.

### Claim 11 (depends on 1)

A metallic oxide thin film transistor manufactured by the method according to claim 1, wherein source and drain electrodes of the thin film transistor are connected to an oxide active layer which is not covered by the etch stopping layer.

### Claim 12 (depends on 11)

The metallic oxide thin film transistor according to claim 11, wherein the etch stopping layer is made of TiO2 or a mixture of TiO2 and CeO2.

### Claim 13 (depends on 11)

The metallic oxide thin film transistor according to claim 11, wherein the etch stopping layer is of a thickness of about 1000 Å to about 6000 Å.

### Claim 14 (depends on 12)

The metallic oxide thin film transistor according to claim 12, wherein based on a total weight of the mixture of TiO2 and CeO2, TiO2 is of a content of about 40 wt % to about 50 wt %.

### Claim 15 (depends on 11)

The metallic oxide thin film transistor according to claim 11, wherein the oxide active layer is made of indium gallium zinc oxide, indium tin zinc oxide or nitrogen zinc oxide, and the oxide active layer is of a thickness of about 500 Å to about 5000 Å.

### Claim 16 (depends on 11)

The metallic oxide thin film transistor according to claim 11, comprising:
a base substrate;
the gate electrode and the gate line located on the base substrate;
the gate insulating layer located on the base substrate formed with the gate electrode and the gate line;
the patters of the oxide active layer and the etch stopping layer located on the gate insulating layer; and
the source electrode, the drain electrode and the data line located on the base substrate formed with the patterns of the oxide active layer and the etch stopping layer.

### Claim 17 (depends on 11)

An array substrate, comprising the metallic oxide thin film transistor according to claim 11, a passivation layer with a via hole located on the base substrate formed with the source electrode, the drain electrode and the data line; and a pixel electrode on the passivation layer, wherein the pixel electrode is connected to the drain electrode through the via hole.

### Claim 18 (depends on 17)

A display device, comprising an array substrate according to claim 17.

### Claim 19 (depends on 9)

A method for manufacturing a metallic oxide thin film transistor array substrate, comprising: after manufacturing the metallic oxide thin film transistor according to claim 9, forming a passivation layer with a via hole on the substrate formed with a source electrode, a drain electrode and a data line through a one-time patterning process; and forming a pixel electrode on the passivation layer through a one-time patterning process, wherein the pixel electrode is connected to the drain electrode through the via hole.

### Claim 20 (depends on 9)

A metallic oxide thin film transistor manufactured by the method according to claim 9, wherein source and drain electrodes of the thin film transistor are connected to an oxide active layer which is not covered by the etch stopping layer.