# US 2016/0365136 A1 · Stacked semiconductor device

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- Number: US 2016/0365136 A1
- Document ID: US20160365136A1
- Status: Published application
- Kind: A1
- Application number: 15/175,933
- Filed: 2016-06-07
- Published: 2016-12-15
- Earliest claimed: 2009-10-23
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Frederick A. Ware
- Web page: https://patentgrep.com/patent/US20160365136A1

## CPC

- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 17/16: using electrically-fusible links
- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- H10W 90/00: Package configurations
- H10W 72/01: {Manufacture or treatment}
- H10W 72/071: {Connecting or disconnecting}
- H10W 72/90: Bond pads, in general
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 80/163: {using active alignment, e.g. detecting marks and correcting position}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.

## Claims

### Claim 1

(canceled)

### Claim 2

A memory device for coupling with a logic integrated circuit (IC) chip having a first input/output (I/O) circuit, the memory device comprising:
a first memory IC chip having a second I/O circuit formed at a first location on the first memory IC chip;
a second memory IC chip stacked with the first memory IC chip, the second memory IC chip including a third I/O circuit formed at a second location on the second memory IC chip that corresponds to the first location on the first memory IC chip; and
a link for establishing a point-to-point connection between the first I/O circuit and one of the second I/O circuit or the third I/O circuit.

### Claim 3 (depends on 2)

The memory device according to claim 2, wherein the first and second memory IC chips comprise DRAM memory devices.

### Claim 4 (depends on 3)

The memory according to claim 3, wherein the logic IC chip comprises a DRAM memory controller.

### Claim 5 (depends on 2)

The memory according to claim 2, wherein the link comprises a through-silicon-via (TSV).

### Claim 6 (depends on 2)

The memory according to claim 2, wherein the second I/O circuit of the first memory IC is vertically aligned with the third I/O circuit of the second memory IC, and the link is for connecting the first I/O circuit to the third I/O circuit and not the second I/O circuit.

### Claim 7 (depends on 6)

The memory according to claim 6, wherein the link connects to the third I/O via a programmable fuse.

### Claim 8 (depends on 2)

The memory according to claim 2, wherein the stacking of the first memory IC is laterally offset with respect to the second memory IC such that the third I/O circuit is misaligned with the second I/O circuit.

### Claim 9 (depends on 2)

The memory device according to claim 2, wherein each of the first and second memory IC chips further includes respective control/address I/O circuits, and wherein the memory device further comprises a multi-drop link coupled to the respective control/address I/O circuits.

### Claim 10 (depends on 2)

The memory device according to claim 2, wherein the first and second memory IC chips comprise non-volatile memory devices.

### Claim 11

A memory comprising:
a logic integrated circuit (IC) chip having a first input/output (I/O) circuit;
a first memory IC chip stacked with the logic IC chip and having a second I/O circuit formed at a first location on the first memory IC chip;
a second memory IC chip stacked with the first memory IC chip, the second memory chip including a third I/O circuit formed at a second location on the second memory IC chip that corresponds to the first location on the first memory IC chip; and
a point-to-point link connecting the first I/O circuit to the third I/O circuit.

### Claim 12 (depends on 11)

The memory according to claim 11, wherein the first and second memory IC chips comprise DRAM memory devices.

### Claim 13 (depends on 11)

The memory according to claim 11, wherein the logic IC chip comprises a DRAM memory controller.

### Claim 14 (depends on 11)

The memory according to claim 11, wherein the point-to-point link comprises a through-silicon-via (TSV).

### Claim 15 (depends on 11)

The memory according to claim 11, wherein the second I/O circuit of the first memory IC is vertically aligned with the third I/O circuit of the second memory IC, and the point-to-point link connects the first I/O circuit to the third I/O circuit and not the second I/O circuit.

### Claim 16 (depends on 15)

The memory according to claim 15, wherein the point-to-point link connects to the third I/O via a programmable fuse.

### Claim 17 (depends on 11)

The memory according to claim 11, wherein the stacking of the first memory IC is laterally offset with respect to the second memory IC such that the third I/O circuit vertically aligns with the first I/O circuit, and the second I/O circuit is offset from the first I/O circuit.

### Claim 18 (depends on 11)

The memory according to claim 11, wherein each of the logic and first and second memory IC chips further includes respective control/address I/O circuits, and wherein the memory further comprises a multi-drop link coupled to the respective control/address I/O circuits.

### Claim 19 (depends on 11)

The memory according to claim 11, wherein the first and second memory IC chips comprise non-volatile memory devices.

### Claim 20

A method of operating a memory having a memory controller IC chip stacked with multiple memory device IC chips, the method comprising:
transferring data signals between the memory controller IC chip and each of the multiple memory device IC chips along through-silicon via point-to-point links; and
transferring control/address (C/A) signals between the memory controller IC chip and each of the memory device IC chips along at least one through-silicon via multi-drop link.

### Claim 21 (depends on 20)

The method according to claim 20, wherein the transferring data signals and transferring C/A signals is carried out in accordance with a DRAM protocol.