# US 2016/0355398 A1 · Semiconductor Device and Method for Manufacturing the Same

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- Number: US 2016/0355398 A1
- Document ID: US20160355398A1
- Status: Published application
- Kind: A1
- Application number: 14/731,433
- Filed: 2015-06-05
- Published: 2016-12-08
- Earliest claimed: 2015-06-05
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corporation
- Inventors: YAN-DA CHEN; WENG YI CHEN; CHANG-SHENG HSU; KUAN-YU WANG; YUAN SHENG LIN
- Web page: https://patentgrep.com/patent/US20160355398A1

## CPC

- H10P 14/60: of insulating materials
- B81C 1/00801: {Avoid alteration of functional structures by etching, e.g. using a passivation layer or an etch stop layer (B81C1/00595, B81C1/00468 take precedence)}
- B81B 2207/015: the micromechanical device and the control or processing electronics being integrated on the same substrate
- B81C 2201/014: by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal
- B81C 2201/016: Passivation
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01)
- B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided herein is a semiconductor device is provided. The semiconductor device includes a substrate including a MEMS region and a connection region thereon; a dielectric layer disposed on the substrate in the connection region; a poly-silicon layer disposed on the dielectric layer, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer; and a passivation layer covering the dielectric layer, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate comprising a MEMS region and a connection region thereon;
a dielectric layer disposed on said substrate in said connection region;
a poly-silicon layer disposed on said dielectric layer, wherein said poly-silicon layer serves as an etch-stop layer;
a connection pad disposed on said poly-silicon layer; and
a passivation layer covering said dielectric layer, wherein the passivation layer comprises an opening that exposes said connection pad and a transition region between said connection pad and said passivation layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a conductive layer covering said connection pad and said poly-silicon layer in said transition region.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein said conductive layer comprises a single layer comprising metal, conductive oxide, conductive nitride or combination thereof.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein said conductive layer comprises multiple layers comprising metal, conductive oxide, conductive nitride or combination thereof.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein said MEMS region comprises a plurality of holes and at least one MEMS diaphragm carried by said substrate.

### Claim 6

A method for manufacturing a semiconductor device, comprising:
providing a substrate comprising a MEMS region and a connection region thereon;
providing a dielectric layer disposed on said substrate in said connection region;
providing a poly-silicon layer disposed on said dielectric layer, wherein said poly-silicon layer serves as an etch-stop layer;
providing a connection pad disposed on said poly-silicon layer; and
providing a passivation layer covering said dielectric layer, wherein the passivation layer comprises an opening that exposes said connection pad and a transition region between said connection pad and said passivation layer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising a step of providing a conductive layer covering said connection pad and said poly-silicon layer in said transition region.

### Claim 8 (depends on 7)

The method of claim 7, wherein said conductive layer comprises a single layer comprising metal, conductive oxide, conductive nitride or combination thereof.

### Claim 9 (depends on 7)

The method of claim 7, wherein said conductive layer comprises multiple layers comprising metal, conductive oxide, conductive nitride or combination thereof.

### Claim 10 (depends on 6)

The method of claim 6, wherein said MEMS region comprises a plurality of sealed micromachined mesh membranes carried by said substrate.