# US 2016/0355393 A1 · Chip package and manufacturing method thereof

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- Number: US 2016/0355393 A1
- Document ID: US20160355393A1
- Status: Published application
- Kind: A1
- Application number: 15/171,971
- Filed: 2016-06-02
- Published: 2016-12-08
- Earliest claimed: 2015-06-08
- Assignees: Xintec Inc.
- Applicants: Xintec Inc.
- Inventors: Tsang-Yu LIU; Wei-Luen SUEN; Po-Han LEE
- Web page: https://patentgrep.com/patent/US20160355393A1

## CPC

- B81B 3/0081: {Thermal properties}
- B81B 7/0077: {Other packages not provided for in groups B81B7/0035 - B81B7/0074}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes}
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A chip package includes a chip having an upper surface and a lower surface. A sensing element is disposed on the upper surface of the chip, and a thermal dissipation layer is disposed below the lower surface of the chip. A plurality of thermal dissipation external connections are disposed below the thermal dissipation layer and in contact with the thermal dissipation layer.

## Claims

### Claim 1

A chip package, comprising:
a chip having an upper surface and a lower surface;
a sensing element disposed at the upper surface;
a thermal dissipation layer disposed at the lower surface; and
a plurality of thermal dissipation external connections disposed underneath and in contact with the thermal dissipation layer.

### Claim 2 (depends on 1)

The chip package of claim 1, wherein the thermal dissipation layer is disposed at a place corresponding to the lower surface of the sensing element.

### Claim 3 (depends on 1)

The chip package of claim 1, further comprising:
an insulating layer disposed at the lower surface and covering the thermal dissipation layer; and
a protective layer disposed at the lower surface and covering the insulating layer, a lower surface of the protective layer has a plurality of openings penetrating the protective layer and the insulating layer, and exposing the thermal dissipation layer,
wherein the thermal dissipation external connections are disposed within the openings and in contact with the thermal dissipation layer.

### Claim 4 (depends on 1)

The chip package of claim 1, wherein the material of the thermal dissipation layer is a metal material.

### Claim 5 (depends on 4)

The chip package of claim 4, wherein the metal material is aluminum.

### Claim 6 (depends on 1)

The chip package of claim 1, wherein the thickness of the thermal dissipation layer is between 1 μm and 1.5 μm.

### Claim 7 (depends on 1)

The chip package of claim 1, wherein the thermal dissipation external connections are solder balls.

### Claim 8

A method of manufacturing a chip package, the method comprising:
providing a wafer having an upper surface, a lower surface, and a plurality of chips, wherein each of the chips comprises a sensing element disposed at the upper surface;
forming a thermal dissipation layer at the lower surface;
forming an insulating layer covering the thermal dissipation layer;
removing a portion of the insulating layer to expose the thermal dissipation layer;
forming a protective layer covering the insulating layer and the thermal dissipation layer;
removing a portion of the protective layer to expose the thermal dissipation layer; and
forming a plurality of thermal dissipation external connections underneath and in contact with the thermal dissipation layer.

### Claim 9 (depends on 8)

The method of manufacturing the chip package of claim 8, wherein the chip further comprises a conductive pad disposed underneath the upper surface and electrically connected to the sensing element.

### Claim 10 (depends on 9)

The method of manufacturing the chip package of claim 9, further comprising forming a plurality of openings in the wafer, wherein the openings extends from the lower surface toward the upper surface and exposes the conductive pad.

### Claim 11 (depends on 10)

The method of manufacturing the chip package of claim 10, wherein the insulating layer covers sidewalls of the openings and the conductive pad.

### Claim 12 (depends on 11)

The method of manufacturing the chip package of claim 11, wherein removing the portion of the insulating layer to expose the thermal dissipation layer further comprises:
removing a portion of the insulating layer to expose the conductive pad.

### Claim 13 (depends on 8)

The method of manufacturing the chip package of claim 8, further comprising forming a conductive layer underneath the insulating layer, wherein the protective layer covers the conductive layer.

### Claim 14 (depends on 13)

The method of manufacturing the chip package of claim 13, wherein removing the portion of the protective layer to expose the thermal dissipation layer further comprises:
removing a portion of the protective layer to expose the conductive layer.

### Claim 15 (depends on 14)

The method of manufacturing the chip package of claim 14, further comprising forming a plurality of conductive connections underneath and in contact with the conductive layer, wherein the thermal dissipation external connections and the conductive connections are solder balls and are formed meanwhile in the same process step.

### Claim 16 (depends on 8)

The method of manufacturing the chip package of claim 8, further comprising separating two adjacent chips along a scribe line to form a chip package.