Pipelined cascaded digital signal processing structures and methods
AssigneeAltera Corporation
InventorMartin Langhammer
Life of this patent
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Abstract
Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.
Claims25
Circuitry accepting a data input and generating a data output based on said data input, said circuitry comprising:
- a first circuit block, including:
- a first multiplier circuit,
- a first plurality of pipeline registers that pipeline an operation of the first multiplier circuit,
- a first adder circuit accepting a first adder input from within the first circuit block, and a second adder input from a first interblock connection;
- and
- a second circuit block cascaded to the first circuit block via the first interblock connection, including:
- a second multiplier circuit,
- a second plurality of pipeline registers that pipeline an operation of the second multiplier circuit, wherein
- the second plurality of pipeline registers has a first selectable connection configuration such that one or more of the second plurality of pipeline registers are configured to be selectively bypassed to balance the first adder input and the second adder input.
Circuitry operating under a floating-point mode or a fixed-point mode, said circuitry comprising:
- a first circuit accepting a first data input and generating a first data output, the first circuit including:
- a first arithmetic element accepting the first data input,
- a plurality of pipeline registers disposed in connection with the first arithmetic element, and
- a cascade register that outputs the first data output;
- and
- a second circuit accepting a second data input and generating a second data output, wherein:
- the second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register, and
- the cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.
Circuitry operating under a recursive-vector mode, comprising:
- a first circuit accepting a first input and a first interblock input, and generating a first output;
- a second circuit cascaded to the first circuit, wherein:
- the second circuit accepts a second input and a second interblock input, and outputs the first interblock input via a first cascade register to the first circuit,
- the first cascade register is connected to a plurality of pipeline registers, and
- a pipeline register from the plurality of pipeline registers is selectively bypassed when the first cascade register is used;
- and
- a third circuit cascaded to the second circuit, wherein
- the third circuit accepts a third input, and outputs the second interblock input to the second circuit and a third output;
- wherein:
- the first output is connected to the third input, and
- the third output is connected to the second input.
A method of operating cascaded circuitry, comprising:
- receiving, via a plurality of input registers within a first circuit, a data input signal, wherein
- the first circuit includes:
- a first arithmetic element that supports floating-point operation,
- a plurality of pipeline registers that pipeline an operation of the first arithmetic element, and
- a cascade register that is connected to a second circuit;
- receiving, from a processor, a first command signal to use the cascade register;
- and
- in response to the first command signal:
- selectively bypassing an input register from the plurality of input registers, or a pipeline register from the plurality of pipeline registers to compensate for a delay from the cascade register, and
- transmitting, via the cascade register, an interblock data signal from the first circuit to the second circuit.
Dependencies are inferred from the claim text.