Semiconductor device, memory circuit, method of manufacturing semiconductor device

A memory circuit provided with a switch element and one of a non-volatile element and a volatile element, the switch element being configured to control a current flowing through one of the non-volatile element and the volatile element, the switch element comprising:

• a first diffusion section in a semiconductor layer having a groove, the first diffusion section formed at or in the vicinity of a bottom of the groove;
• a second diffusion section formed at an upper end of the groove in the semiconductor layer;
• a channel section formed between the first diffusion section and the second diffusion section in the semiconductor layer;
• a gate section buried in the groove at a position opposing the channel section;
• a first electrode section electrically coupled to the first diffusion section, and provided on rear surface side of the semiconductor layer;
• a second electrode section electrically coupled to the second diffusion section, and provided on top surface side of the semiconductor layer;
• a third electrode section electrically coupled to the gate section, and provided on the top surface side of the semiconductor layer;
• and
• a stress application section configured to apply one of compressive stress and tensile stress to the channel section in a normal direction to the semiconductor layer.

A method of manufacturing a semiconductor device, the method comprising:

• forming, in a semiconductor layer having a groove, a first diffusion section through the groove and forming a second diffusion section, thereby forming a channel section between the first diffusion section and second diffusion section, the first diffusion section being formed at a bottom of the groove, and the second diffusion section being formed at an upper end of the groove;
• forming a gate insulating film on an entire surface including an inner surface of the groove, followed by forming a gate section and removing a part protruding from the groove of the gate insulating film, the gate insulating film being made of a high-k material having a higher relative dielectric constant than a relative dielectric constant of a silicon oxide, and the gate section being made of a metal material and formed at a position opposing the channel section in the groove;
• forming a stress application section, the stress application section being configured to apply one of compressive stress and tensile stress to the channel section in a normal direction to the semiconductor layer;
• and
• forming a first electrode section, a second electrode section, and a third electrode section, the first electrode section being provided on rear surface side of the semiconductor layer and being electrically coupled to the first diffusion section, the second electrode section being provided on top surface side of the semiconductor layer and being electrically coupled to the second diffusion section, and the third electrode section being provided on the top surface side of the semiconductor layer and being electrically coupled to the gate section.