Autoconfigurable Phase-Locked Loop Which Automatically Maintains a Constant Damping Factor and Adjusts the Loop Bandwidth to a Constant Ratio of the Reference Frequency

A phase-locked loop (PLL), comprising:

• a frequency detector circuit for estimating a frequency of a reference frequency signal by counting a number of cycles of the reference frequency signal over a fixed period of time;
• a phase detector for generating up and down command signals in response to phase differences between the reference frequency signal and a frequency signal related to a base PLL output frequency signal;
• a circuit for producing control signals in dependence upon the frequency detected by said frequency detector;
• a charge-pump DAC for generating a charge-pump current, said charge-pump DAC being connected to receive said up and down command signals and control signals from said circuit for producing control signals to produce a charge-pump output current of magnitude selected by said control signals from said circuit for producing control signals;
• an integrator for integrating said charge-pump output current, said integrator including having plurality of capacitors switchably selected by control signals from said circuit for producing control signals to produce an integrating capacitance value;
• and
• a voltage controlled oscillator (VCO) for producing the base PLL output frequency signal in response to said integrated charge-pump output signal.